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GraVF-M

https://doi.org/10.1145/3357596
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Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/asap.2012.30openalex-snapshot
A Reconfigurable Computing Approach for Efficient and Scalable Parallel Graph Exploration
inferredcites →https://doi.org/10.1109/asap.2015.7245698openalex-snapshot
Custom FPGA-based soft-processors for sparse graph acceleration
inferredcites →https://doi.org/10.1109/ccgrid.2017.114openalex-snapshot
TuNao: A High-Performance and Energy-Efficient Reconfigurable Accelerator for Graph Processing
inferredcites →https://doi.org/10.1109/fccm.2006.45openalex-snapshot
GraphStep: A System Architecture for Sparse-Graph Algorithms
inferredcites →https://doi.org/10.1109/fccm.2014.15openalex-snapshot
GraphGen: An FPGA Framework for Vertex-Centric Graph Computation
inferredcites →https://doi.org/10.1109/fccm.2016.35openalex-snapshot
High-Throughput and Energy-Efficient Graph Processing on FPGA
inferredcites →https://doi.org/10.1109/fpl.2015.7293939openalex-snapshot
Hybrid breadth-first search on a single-chip FPGA-CPU heterogeneous platform
inferredcites →https://doi.org/10.1109/fpl.2016.7577360openalex-snapshot
GraVF: A vertex-centric distributed graph processing framework on FPGAs
inferredcites →https://doi.org/10.1109/fpl.2018.00043openalex-snapshot
Performance-Driven System Generation for Distributed Vertex-Centric Graph Processing on Multi-FPGA Systems
inferredcites →https://doi.org/10.1109/fpt.2010.5681757openalex-snapshot
A message-passing multi-softcore architecture on FPGA for Breadth-first Search
inferredcites →https://doi.org/10.1109/fpt.2011.6132667openalex-snapshot
A framework for FPGA acceleration of large graph problems: Graphlet counting case study
inferredcites →https://doi.org/10.1109/ipdpsw.2014.30openalex-snapshot
CyGraph: A Reconfigurable Architecture for Parallel Breadth-First Search
inferredcites →https://doi.org/10.1109/reconfig.2015.7393284openalex-snapshot
Accelerating all-pairs shortest path using a message-passing reconfigurable architecture
inferredcites →https://doi.org/10.1109/sbac-pad.2017.25openalex-snapshot
Accelerating Graph Analytics on CPU-FPGA Heterogeneous Platform
inferredcites →https://doi.org/10.1137/1.9781611972740.43openalex-snapshot
R-MAT: A Recursive Model for Graph Mining
inferredcites →https://doi.org/10.1137/s1064827595287997openalex-snapshot
A Fast and High Quality Multilevel Scheme for Partitioning Irregular Graphs
inferredcites →https://doi.org/10.1145/2019583.2019584openalex-snapshot
Spatial hardware implementation for sparse graph algorithms in GraphStep
inferredcites →https://doi.org/10.1145/2847263.2847337openalex-snapshot
GraphOps
inferredcites →https://doi.org/10.1145/2847263.2847339openalex-snapshot
FPGP
inferredcites →https://doi.org/10.1145/3020078.3021737openalex-snapshot
Boosting the Performance of FPGA-based Graph Processor using Hybrid Memory Cube
inferredcites →https://doi.org/10.1145/3020078.3021739openalex-snapshot
ForeGraph
inferredcites →https://doi.org/10.1145/3020078.3021743openalex-snapshot
FPGA-Accelerated Transactional Execution of Graph Workloads
inferredcites →https://doi.org/10.1145/3120895.3120896openalex-snapshot
Towards Flexible Automatic Generation of Graph Processing Gateware
inferredcites →https://doi.org/10.1145/3174243.3174245openalex-snapshot
Degree-aware Hybrid Graph Traversal on FPGA-HMC Platform
inferredcites →https://doi.org/10.1145/3174243.3174260openalex-snapshot
Accelerating Graph Analytics by Co-Optimizing Storage and Access on an FPGA-HMC Platform
inferredcites →https://doi.org/10.1145/3203217.3203233openalex-snapshot
An FPGA framework for edge-centric graph processing
inferredcites →https://doi.org/10.14778/3137765.3137776openalex-snapshot
ExtraV
inferredcites →https://doi.org/10.5555/305219.305248openalex-snapshot
A Fast and High Quality Multilevel Scheme for Partitioning Irregular Graphs

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-031-62874-0_9openalex-snapshot
Optimising Graph Representation for Hardware Implementation of Graph Convolutional Networks for Event-Based Vision
inferred← citeshttps://doi.org/10.1007/s11390-021-1242-yopenalex-snapshot
FDGLib: A Communication Library for Efficient Large-Scale Graph Processing in FPGA-Accelerated Data Centers
inferred← citeshttps://doi.org/10.1016/j.future.2024.107497openalex-snapshot
HashGrid: An optimized architecture for accelerating graph computing on FPGAs
inferred← citeshttps://doi.org/10.1109/ccgrid57682.2023.00013openalex-snapshot
Rethinking Design Paradigm of Graph Processing System with a CXL-like Memory Semantic Fabric
inferred← citeshttps://doi.org/10.1109/icfpt56656.2022.9974189openalex-snapshot
GraFF: A Multi-FPGA System with Memory Semantic Fabric for Scalable Graph Processing
inferred← citeshttps://doi.org/10.1109/icfpt64416.2024.11113456openalex-snapshot
Swift: A Multi-FPGA Framework for Scaling Up Accelerated Graph Analytics
inferred← citeshttps://doi.org/10.1109/icicm56102.2022.10011381openalex-snapshot
Graph_CC: Accelerator of Connected Component Search in Graph Computing
inferred← citeshttps://doi.org/10.1145/3517141openalex-snapshot
ThunderGP: Resource-Efficient Graph Processing Framework on FPGAs with HLS
inferred← citeshttps://doi.org/10.1145/3725275openalex-snapshot
Clementi: Efficient Load Balancing and Communication Overlap for Multi-FPGA Graph Processing
inferred← citeshttps://doi.org/10.1186/s40537-023-00756-xopenalex-snapshot
Distributed large-scale graph processing on FPGAs
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