On the public citation graph

A pipelined and scalable dataflow implementation of convolutional neural networks on FPGA

https://doi.org/10.1109/ipdpsw.2017.44

0 signed · 46 inferred · view as graph

Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

Is this your work? Sign in with ORCID and put your name on the claims that are yours.

Claim with ORCID

Reference health. See whether every reference in this work resolves to a known work and none has been retracted — and get a dated CiteStamped badge you can embed.

See reference health

What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/5.726791openalex-snapshot

Gradient-based learning applied to document recognition

inferredcites →https://doi.org/10.1109/asap.2009.25openalex-snapshot

A Massively Parallel Coprocessor for Convolutional Neural Networks

inferredcites →https://doi.org/10.1109/fpl.2009.5272559openalex-snapshot

CNP: An FPGA-based processor for Convolutional Networks

inferredcites →https://doi.org/10.1109/iccd.2013.6657019openalex-snapshot

Memory-centric accelerator design for Convolutional Neural Networks

inferredcites →https://doi.org/10.1109/ipdpsw.2016.153openalex-snapshot

On the Automation of High Level Synthesis of Convolutional Neural Networks

inferredcites →https://doi.org/10.1109/iscas.2010.5537907openalex-snapshot

Convolutional networks and applications in vision

inferredcites →https://doi.org/10.1109/micro.2014.58openalex-snapshot

DaDianNao: A Machine-Learning Supercomputer

inferredcites →https://doi.org/10.1109/pdp.2010.43openalex-snapshot

Performance and Scalability of GPU-Based Convolutional Neural Networks

inferredcites →https://doi.org/10.1109/tpami.2012.59openalex-snapshot

3D Convolutional Neural Networks for Human Action Recognition

inferredcites →https://doi.org/10.1145/1273496.1273556openalex-snapshot

An empirical evaluation of deep architectures on problems with many factors of variation

inferredcites →https://doi.org/10.1145/1498765.1498785openalex-snapshot

Roofline

inferredcites →https://doi.org/10.1145/1815961.1815993openalex-snapshot

A dynamically configurable coprocessor for convolutional neural networks

inferredcites →https://doi.org/10.1145/1854273.1854309openalex-snapshot

A programmable parallel accelerator for learning and classification

inferredcites →https://doi.org/10.1145/2505515.2514699openalex-snapshot

Large-scale deep learning at Baidu

inferredcites →https://doi.org/10.1145/2684746.2689060openalex-snapshot

Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks

inferredcites →https://doi.org/10.1145/2842615openalex-snapshot

On How to Accelerate Iterative Stencil Loops

inferredcites →https://doi.org/10.1145/2847263.2847265openalex-snapshot

Going Deeper with Embedded FPGA Platform for Convolutional Neural Network

inferredcites →https://doi.org/10.1145/2966986.2966995openalex-snapshot

A polyhedral model-based framework for dataflow implementation on FPGA devices of iterative stencil loops

inferredcites →https://doi.org/10.1145/2966986.2967011openalex-snapshot

Caffeine

inferredcites →https://doi.org/10.1145/3065386openalex-snapshot

ImageNet classification with deep convolutional neural networks

inferredcites →https://doi.org/10.1145/3603165.3607390openalex-snapshot

Caffeine: Towards Uniformed Representation and Acceleration for Deep Convolutional Neural Networks

inferredcites →https://doi.org/10.48550/arxiv.1408.5093openalex-snapshot

Caffe: Convolutional Architecture for Fast Feature Embedding

inferredcites →https://doi.org/10.48550/arxiv.1409.1556openalex-snapshot

Very Deep Convolutional Networks for Large-Scale Image Recognition

inferredcites →https://doi.org/10.5591/978-1-57735-516-8/ijcai11-210openalex-snapshot

Flexible, high performance convolutional neural networks for image classification

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-030-44534-8_16openalex-snapshot

A Modular Software Library for Effective High Level Synthesis of Convolutional Neural Networks

inferred← citeshttps://doi.org/10.1007/978-3-030-79025-7_20openalex-snapshot

Accelerating Convolutional Neural Networks in FPGA-based SoCs using a Soft-Core GPU

inferred← citeshttps://doi.org/10.1007/s42979-021-00954-5openalex-snapshot

2L-3W: 2-Level 3-Way Hardware–Software Co-verification for the Mapping of Convolutional Neural Network (CNN) onto FPGA Boards

inferred← citeshttps://doi.org/10.1109/access.2020.3041464openalex-snapshot

An Energy-Efficient Implementation of Group Pruned CNNs on FPGA

inferred← citeshttps://doi.org/10.1109/dsmp.2018.8478455openalex-snapshot

Implementation of Neural Networks with Help of a Data Flow Virtual Machine

inferred← citeshttps://doi.org/10.1109/icsp.2018.8652487openalex-snapshot

An Exploration of FPGA based Multilayer Perceptron using Residue Number System for Space Applications

inferred← citeshttps://doi.org/10.1109/imcec.2018.8469659openalex-snapshot

FPGA Implementation of Neural Network Accelerator

inferred← citeshttps://doi.org/10.1109/ipdpsw.2018.00033openalex-snapshot

A Framework with Cloud Integration for CNN Acceleration on FPGA Devices

inferred← citeshttps://doi.org/10.1109/ipdpsw.2019.00026openalex-snapshot

Deep Learning in Reconfigurable Hardware: A Survey

inferred← citeshttps://doi.org/10.1109/ipdpsw.2019.00028openalex-snapshot

Pareto Optimal Design Space Exploration for Accelerated CNN on FPGA

inferred← citeshttps://doi.org/10.1109/iscas.2018.8351425openalex-snapshot

A Reconfigurable Pipelined Architecture for Convolutional Neural Network Acceleration

inferred← citeshttps://doi.org/10.1109/isdcs.2019.8719278openalex-snapshot

Hardware Efficient Convolution Processing Unit for Deep Neural Networks

inferred← citeshttps://doi.org/10.1145/3194554.3194627openalex-snapshot

Dataflow-Based Mapping of Spiking Neural Networks on Neuromorphic Hardware

inferred← citeshttps://doi.org/10.1145/3372799.3394364openalex-snapshot

Compiling Spiking Neural Networks to Neuromorphic Hardware

inferred← citeshttps://doi.org/10.1145/3461648.3463846openalex-snapshot

CHaNAS: coordinated search for network architecture and scheduling policy

inferred← citeshttps://doi.org/10.1145/3479156openalex-snapshot

DFSynthesizer: Dataflow-based Synthesis of Spiking Neural Networks to Neuromorphic Hardware

inferred← citeshttps://doi.org/10.1145/3533251openalex-snapshot

A Framework for Neural Network Architecture and Compile Co-optimization

inferred← citeshttps://doi.org/10.1145/3652861openalex-snapshot

CuMONITOR: Continuous Monitoring of Microarchitecture for Software Task Identification and Classification

inferred← citeshttps://doi.org/10.20334/2021-021-mopenalex-snapshot

Edge computing tied in artificial neural network classifiers

inferred← citeshttps://doi.org/10.21203/rs.3.rs-4519028/v1openalex-snapshot

Edge-Side Highly Configurable Accelerator With Efficient Automatic Structure Search Scheme

inferred← citeshttps://doi.org/10.48550/arxiv.1911.05944openalex-snapshot

2L-3W: 2-Level 3-Way Hardware-Software Co-Verification for the Mapping of Deep Learning Architecture (DLA) onto FPGA Boards

inferred← citeshttps://doi.org/10.70675/2609bad0z35acz4e0dz9fa3zd4505963159dopenalex-snapshot

Performance of a Neural Network Accelerator Architecture and its Optimization Using a Pipeline-Based Approach

Editorial review for independent work. ICSAC — the Institute for Complexity Science and Advanced Computing — runs a structured editorial panel for researchers publishing outside journals, and publishes on CiteStamp rails. Submission is free and goes through ORCID: icsacinstitute.org/submit.