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Evolution, challenge, and outlook of TSV, 3D IC integration and 3d silicon integration

https://doi.org/10.1109/isapm.2011.6105753
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Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-1-4615-3910-0openalex-snapshot
Solder Joint Reliability
inferredcites →https://doi.org/10.1016/j.microrel.2010.03.010openalex-snapshot
Design, assembly and reliability of large die and fine-pitch Cu/low-k flip chip package
inferredcites →https://doi.org/10.1016/j.sna.2009.01.024openalex-snapshot
Application of piezoresistive stress sensors in ultra thin device handling and characterization
inferredcites →https://doi.org/10.1049/el:20080661openalex-snapshot
Three-dimensional integration of silicon-on-insulator RF amplifier
inferredcites →https://doi.org/10.1063/1.90501openalex-snapshot
cw laser anneal of polycrystalline silicon: Crystalline structure, electrical properties
inferredcites →https://doi.org/10.1108/03056129710370132openalex-snapshot
Design for Plastic Ball Grid Array Solder Joint Reliability
inferredcites →https://doi.org/10.1108/09540919810203829openalex-snapshot
Solder joint reliability of cavity‐down plastic ball grid array assemblies
inferredcites →https://doi.org/10.1108/13565361011034786openalex-snapshot
3D LED and IC wafer level packaging
inferredcites →https://doi.org/10.1108/13565361111127304openalex-snapshot
Overview and outlook of through‐silicon via (TSV) and 3D integrations
inferredcites →https://doi.org/10.1108/mi.2003.21820aae.004openalex-snapshot
Microvias for Low Cost High Density Interconnects
inferredcites →https://doi.org/10.1109/96.544363openalex-snapshot
Solder joint reliability of flip chip and plastic ball grid array assemblies under thermal, mechanical, and vibrational conditions
inferredcites →https://doi.org/10.1109/96.659504openalex-snapshot
Electrical design of a cost-effective thermal enhanced plastic ball grid array package-NuBGA
inferredcites →https://doi.org/10.1109/cpmtsympj.2010.5679528openalex-snapshot
Development of high accuracy wafer thinning and pickup technology for thin wafer(die)
inferredcites →https://doi.org/10.1109/cpmtsympj.2010.5679530openalex-snapshot
Room-temperature Si-Si and Si-SiN wafer bonding
inferredcites →https://doi.org/10.1109/cpmtsympj.2010.5679531openalex-snapshot
Guard ring effect for through silicon via (TSV) noise coupling reduction
inferredcites →https://doi.org/10.1109/cpmtsympj.2010.5679532openalex-snapshot
Thermal stress analysis of 3D die stacks with low-volume interconnections
inferredcites →https://doi.org/10.1109/cpmtsympj.2010.5679534openalex-snapshot
Wafer and/or chip bonding adhesives for 3D package
inferredcites →https://doi.org/10.1109/cpmtsympj.2010.5679652openalex-snapshot
Development of Super Thin TSV PoP
inferredcites →https://doi.org/10.1109/cpmtsympj.2010.5679979openalex-snapshot
Evaluation of surface microroughness for surface activated bonding
inferredcites →https://doi.org/10.1109/ectc.2000.853403openalex-snapshot
Silicon interposer technology for high-density package
inferredcites →https://doi.org/10.1109/ectc.2006.1645835openalex-snapshot
Novel Low Cost Integration of Through Chip Interconnection and Application to CMOS Image Sensor
inferredcites →https://doi.org/10.1109/ectc.2006.1645903openalex-snapshot
Effective Thermal Via and Decoupling Capacitor Insertion For 3D System-On-Package
inferredcites →https://doi.org/10.1109/ectc.2007.373945openalex-snapshot
Power Delivery Network Design for 3D SIP Integrated over Silicon Interposer Platform
inferredcites →https://doi.org/10.1109/ectc.2008.4549988openalex-snapshot
A novel, wafer-level stacking method for low-chip yield and non-uniform, chip-size wafers for MEMS and 3D SIP applications
inferredcites →https://doi.org/10.1109/ectc.2008.4550025openalex-snapshot
3D silicon integration
inferredcites →https://doi.org/10.1109/ectc.2008.4550027openalex-snapshot
Development of 3D silicon module with TSV for system in packaging
inferredcites →https://doi.org/10.1109/ectc.2008.4550030openalex-snapshot
A Silicon interposer BGA package with Cu-filled TSV and multi-layer Cu-plating interconnect
inferredcites →https://doi.org/10.1109/ectc.2008.4550074openalex-snapshot
Through silicon via technology — processes and reliability for wafer-level 3D system integration
inferredcites →https://doi.org/10.1109/ectc.2008.4550075openalex-snapshot
Silicon interposer with TSVs (Through Silicon Vias) and fine multilayer wiring
inferredcites →https://doi.org/10.1109/ectc.2008.4550108openalex-snapshot
Nonlinear thermal stress/strain analyses of copper filled TSV (through silicon via) and their flip-chip microbumps
inferredcites →https://doi.org/10.1109/ectc.2008.4550177openalex-snapshot
Effect of wafer back grinding on the mechanical behavior of multilayered low-k for 3D-stack packaging applications
inferredcites →https://doi.org/10.1109/ectc.2008.4550249openalex-snapshot
High RF performance TSV silicon carrier for high frequency application
inferredcites →https://doi.org/10.1109/ectc.2009.5073988openalex-snapshot
Study of 15µm pitch solder microbumps for 3D IC integration
inferredcites →https://doi.org/10.1109/ectc.2009.5074032openalex-snapshot
Development of through silicon via (TSV) interposer technology for large die (21×21mm) fine-pitch Cu/low-k FCBGA package
inferredcites →https://doi.org/10.1109/ectc.2009.5074036openalex-snapshot
Development of novel intermetallic joints using thin film indium based solder by low temperature bonding technology for 3D IC stacking
inferredcites →https://doi.org/10.1109/ectc.2009.5074039openalex-snapshot
Three dimensional interconnects with high aspect ratio TSVs and fine pitch solder microbumps
inferredcites →https://doi.org/10.1109/ectc.2009.5074080openalex-snapshot
Thermal management of 3D IC integration with TSV (through silicon via)
inferredcites →https://doi.org/10.1109/ectc.2009.5074115openalex-snapshot
A novel moiré fringe assisted method for nanoprecision alignment in wafer bonding
inferredcites →https://doi.org/10.1109/ectc.2009.5074132openalex-snapshot
Development of 3-D silicon die stacked package using flip chip technology with micro bump interconnects
inferredcites →https://doi.org/10.1109/ectc.2009.5074157openalex-snapshot
3D packaging with through ilicon via (TSV) for electrical and fluidic interconnections
inferredcites →https://doi.org/10.1109/ectc.2009.5074199openalex-snapshot
3D image sensor SiP with TSV silicon interposer
inferredcites →https://doi.org/10.1109/ectc.2010.5490636openalex-snapshot
3D chip stacking & reliability using TSV-micro C4 solder interconnection
inferredcites →https://doi.org/10.1109/ectc.2010.5490637openalex-snapshot
Evaluation of thin wafer processing using a temporary wafer handling system as key technology for 3D system integration
inferredcites →https://doi.org/10.1109/ectc.2010.5490639openalex-snapshot
Low temperature bump-less Cu-Cu bonding enhancement with self assembled monolayer (SAM) passivation for 3-D integration
inferredcites →https://doi.org/10.1109/ectc.2010.5490641openalex-snapshot
Insertion bonding: A novel Cu-Cu bonding approach for 3D integration
inferredcites →https://doi.org/10.1109/ectc.2010.5490643openalex-snapshot
Vertical metal interconnect thanks to tungsten direct bonding
inferredcites →https://doi.org/10.1109/ectc.2010.5490650openalex-snapshot
TSV stress testing and modeling
inferredcites →https://doi.org/10.1109/ectc.2010.5490686openalex-snapshot
Three chips stacking with low volume solder using single re-flow process
inferredcites →https://doi.org/10.1109/ectc.2010.5490688openalex-snapshot
Yield modeling of 3D integrated wafer scale assemblies
inferredcites →https://doi.org/10.1109/ectc.2010.5490692openalex-snapshot
Modified diffusion bonding for both Cu and SiO2 at 150 °C in ambient air
inferredcites →https://doi.org/10.1109/ectc.2010.5490697openalex-snapshot
Copper direct bonding: An innovative 3D interconnect
inferredcites →https://doi.org/10.1109/ectc.2010.5490698openalex-snapshot
Cu/Sn microbumps interconnect for 3D TSV chip stacking
inferredcites →https://doi.org/10.1109/ectc.2010.5490702openalex-snapshot
High temperature resistant bonding solutions enabling thin wafer processing (Characterization of polyimide base temporary bonding adhesive for thinned wafer handling)
inferredcites →https://doi.org/10.1109/ectc.2010.5490703openalex-snapshot
IMC bonding for 3D interconnection
inferredcites →https://doi.org/10.1109/ectc.2010.5490704openalex-snapshot
High density interconnect at 10µm pitch with mechanically keyed Cu/Sn-Cu and Cu-Cu bonding for 3-D integration
inferredcites →https://doi.org/10.1109/ectc.2010.5490707openalex-snapshot
Characterization and management of wafer stress for various pattern densities in 3D integration technology
inferredcites →https://doi.org/10.1109/ectc.2010.5490709openalex-snapshot
Intermetallic Cu3Sn as oxidation barrier for fluxless Cu-Sn bonding
inferredcites →https://doi.org/10.1109/ectc.2010.5490731openalex-snapshot
Integrated process for defect-free copper plating and chemical-mechanical polishing of through-silicon vias for 3D interconnects
inferredcites →https://doi.org/10.1109/ectc.2010.5490746openalex-snapshot
Low temperature PECVD of dielectric films for TSV applications
inferredcites →https://doi.org/10.1109/ectc.2010.5490748openalex-snapshot
Process solutions and polymer materials for 3D-WLP through silicon via filling
inferredcites →https://doi.org/10.1109/ectc.2010.5490749openalex-snapshot
Development of novel carbon nanotube TSV technology
inferredcites →https://doi.org/10.1109/ectc.2010.5490753openalex-snapshot
Power delivery system architecture for many-tier 3D systems
inferredcites →https://doi.org/10.1109/ectc.2010.5490794openalex-snapshot
Efficient full-wave modeling of high density TSVs for 3D integration
inferredcites →https://doi.org/10.1109/ectc.2010.5490799openalex-snapshot
Slow wave and dielectric quasi-TEM modes of Metal-Insulator-Semiconductor (MIS) structure Through Silicon Via (TSV) in signal propagation and power delivery in 3D chip package
inferredcites →https://doi.org/10.1109/ectc.2010.5490807openalex-snapshot
Low-impedance evaluation of power distribution network for decoupling capacitor embedded interposers of 3-D integrated LSI system
inferredcites →https://doi.org/10.1109/ectc.2010.5490820openalex-snapshot
CMOS compatible thin wafer processing using temporary mechanical wafer, adhesive and laser release of thin chips/wafers for 3D integration
inferredcites →https://doi.org/10.1109/ectc.2010.5490828openalex-snapshot
TSV manufacturing yield and hidden costs for 3D IC integration
inferredcites →https://doi.org/10.1109/ectc.2010.5490835openalex-snapshot
Development and characterisation of a 3D technology including TSV and Cu pillars for high frequency applications
inferredcites →https://doi.org/10.1109/ectc.2010.5490838openalex-snapshot
Low-cost TSV process using electroless Ni plating for 3D stacked DRAM
inferredcites →https://doi.org/10.1109/ectc.2010.5490839openalex-snapshot
Electrical characterization of 3D Through-Silicon-Vias
inferredcites →https://doi.org/10.1109/ectc.2010.5490840openalex-snapshot
Adhesion improvement for polymer dielectric to electrolytic-plated copper
inferredcites →https://doi.org/10.1109/ectc.2010.5490841openalex-snapshot
Process characterization vehicles for 3D Integration
inferredcites →https://doi.org/10.1109/ectc.2010.5490882openalex-snapshot
Terabit/s-class 24-channel bidirectional optical transceiver module based on TSV Si carrier for board-level interconnects
inferredcites →https://doi.org/10.1109/ectc.2010.5490883openalex-snapshot
Thermal stress induced delamination of through silicon vias in 3-D interconnects
inferredcites →https://doi.org/10.1109/ectc.2010.5490884openalex-snapshot
Development of CMOS-process-compatible interconnect technology for 3D-stacking of NAND flash memory chips
inferredcites →https://doi.org/10.1109/ectc.2010.5490885openalex-snapshot
Analysis of carbon nanotube based Through Silicon Vias
inferredcites →https://doi.org/10.1109/ectc.2010.5490887openalex-snapshot
3-D Thin film interposer based on TGV (Through Glass Vias): An alternative to Si-interposer
inferredcites →https://doi.org/10.1109/ectc.2010.5490889openalex-snapshot
Design and fabrication of a reliability test chip for 3D-TSV
inferredcites →https://doi.org/10.1109/ectc.2010.5490902openalex-snapshot
Quantification of micropartial residual stress for mechanical characterization of TSV through nanoinstrumented indentation testing
inferredcites →https://doi.org/10.1109/ectc.2010.5490904openalex-snapshot
Full characterization of Cu/Cu direct bonding for 3D integration
inferredcites →https://doi.org/10.1109/ectc.2010.5490913openalex-snapshot
Through-package-via formation and metallization of glass interposers
inferredcites →https://doi.org/10.1109/ectc.2010.5490917openalex-snapshot
Design and fabrication of bandpass filters in glass interposer with through-package-vias (TPV)
inferredcites →https://doi.org/10.1109/ectc.2010.5490936openalex-snapshot
Influence of bonding atmosphere on low-temperature wafer bonding
inferredcites →https://doi.org/10.1109/ectc.2010.5490939openalex-snapshot
Mitigating heat dissipation and thermo-mechanical stress challenges in 3-D IC using thermal through silicon via (TTSV)
inferredcites →https://doi.org/10.1109/ectc.2010.5490953openalex-snapshot
Carrierless design for handling and processing of ultrathin wafers
inferredcites →https://doi.org/10.1109/ectc.2010.5490956openalex-snapshot
Wafer level embedded System in Package (WL-eSiP) for mobile applications
inferredcites →https://doi.org/10.1109/ectc.2011.5898482openalex-snapshot
Chip-to-wafer (C2W) 3D integration with well-controlled template alignment and wafer-level bonding
inferredcites →https://doi.org/10.1109/ectc.2011.5898483openalex-snapshot
Fluxless bonding for fine-pitch and low-volume solder 3-D interconnections
inferredcites →https://doi.org/10.1109/ectc.2011.5898485openalex-snapshot
Thermal reliability of fine pitch Cu-Cu bonding with self assembled monolayer (SAM) passivation for Wafer-on-Wafer 3D-Stacking
inferredcites →https://doi.org/10.1109/ectc.2011.5898486openalex-snapshot
High density 20μm pitch CuSn microbump process for high-end 3D applications
inferredcites →https://doi.org/10.1109/ectc.2011.5898499openalex-snapshot
Ni/Cu/Sn bumping scheme for fine-pitch micro-bump connections
inferredcites →https://doi.org/10.1109/ectc.2011.5898521openalex-snapshot
Novel anisotropic conductive adhesive for 3D stacking and lead-free PCB packaging — A review
inferredcites →https://doi.org/10.1109/ectc.2011.5898524openalex-snapshot
3D Chip stacking with 50 μm pitch lead-free micro-c4 interconnections
inferredcites →https://doi.org/10.1109/ectc.2011.5898525openalex-snapshot
Development of Super Thin TSV PoP
inferredcites →https://doi.org/10.1109/ectc.2011.5898526openalex-snapshot
Design, simulation and process optimization of AuInSn low temperature TLP bonding for 3D IC Stacking
inferredcites →https://doi.org/10.1109/ectc.2011.5898527openalex-snapshot
Advanced reliability study of TSV interposers and interconnects for the 28nm technology FPGA
inferredcites →https://doi.org/10.1109/ectc.2011.5898529openalex-snapshot
Thru silicon via stacking & numerical characterization for multi-die interconnections using full array & very fine pitch micro C4 bumps
inferredcites →https://doi.org/10.1109/ectc.2011.5898536openalex-snapshot
Electromigration study of micro bumps at Si/Si interface in 3DIC package for 28nm technology and beyond
inferredcites →https://doi.org/10.1109/ectc.2011.5898537openalex-snapshot
Electromigration in Ni/Sn intermetallic micro bump joint for 3D IC chip stacking
inferredcites →https://doi.org/10.1109/ectc.2011.5898566openalex-snapshot
Low-profile 3D silicon-on-silicon multi-chip assembly
inferredcites →https://doi.org/10.1109/ectc.2011.5898567openalex-snapshot
3D Sensor application with open through silicon via technology
inferredcites →https://doi.org/10.1109/ectc.2011.5898568openalex-snapshot
Reliability study of 3D-WLP through silicon via with innovative polymer filling integration
inferredcites →https://doi.org/10.1109/ectc.2011.5898569openalex-snapshot
Ceramics vs. low-CTE organic packaging of TSV silicon interposers
inferredcites →https://doi.org/10.1109/ectc.2011.5898571openalex-snapshot
Design, fabrication and characterization of low-cost glass interposers with fine-pitch through-package-vias
inferredcites →https://doi.org/10.1109/ectc.2011.5898578openalex-snapshot
Glass panel processing for electrical and optical packaging
inferredcites →https://doi.org/10.1109/ectc.2011.5898579openalex-snapshot
Study of the thermo-mechanical behavior of glass interposer for flip chip packaging applications
inferredcites →https://doi.org/10.1109/ectc.2011.5898590openalex-snapshot
Comparison of the electromigration behaviors between micro-bumps and C4 solder bumps
inferredcites →https://doi.org/10.1109/ectc.2011.5898596openalex-snapshot
A fast simulation framework for full-chip thermo-mechanical stress and reliability analysis of through-silicon-via based 3D ICs
inferredcites →https://doi.org/10.1109/ectc.2011.5898601openalex-snapshot
Terabit/sec-class board-level optical interconnects through polymer waveguides using 24-channel bidirectional transceiver modules
inferredcites →https://doi.org/10.1109/ectc.2011.5898603openalex-snapshot
Chip-to-chip communication by optical routing inside a thin glass substrate
inferredcites →https://doi.org/10.1109/ectc.2011.5898608openalex-snapshot
TSV based silicon interposer technology for wafer level fabrication of 3D SiP modules
inferredcites →https://doi.org/10.1109/ectc.2011.5898609openalex-snapshot
Integration of fine-pitched Through-Silicon Vias and Integrated Passive Devices
inferredcites →https://doi.org/10.1109/ectc.2011.5898611openalex-snapshot
Design and demonstration of low cost, panel-based polycrystalline silicon interposer with through-package-vias (TPVs)
inferredcites →https://doi.org/10.1109/ectc.2011.5898612openalex-snapshot
Characterization of the thermal impact of Cu-Cu bonds achieved using TSVs on hot spot dissipation in 3D stacked ICs
inferredcites →https://doi.org/10.1109/ectc.2011.5898629openalex-snapshot
Processing of ultrathin 300 mm wafers with carrierless technology
inferredcites →https://doi.org/10.1109/ectc.2011.5898630openalex-snapshot
How to select adhesive materials for temporary bonding and de-bonding of 200mm and 300mm thin-wafer handling for 3D IC integration?
inferredcites →https://doi.org/10.1109/ectc.2011.5898631openalex-snapshot
Metrology and inspection for process control during bonding and thinning of stacked wafers for manufacturing 3D SIC's
inferredcites →https://doi.org/10.1109/ectc.2011.5898650openalex-snapshot
Integration of TSVs, wafer thinning and backside passivation on full 300mm CMOS wafers for 3D applications
inferredcites →https://doi.org/10.1109/ectc.2011.5898651openalex-snapshot
A study on the 3D-TSV interconnection using wafer-level non-conductive adhesives (NCAs)
inferredcites →https://doi.org/10.1109/ectc.2011.5898652openalex-snapshot
Effects of etch rate on scallop of through-silicon vias (TSVs) in 200mm and 300mm wafers
inferredcites →https://doi.org/10.1109/ectc.2011.5898655openalex-snapshot
Solder/adhesive bonding using simple planarization technique for 3D integration
inferredcites →https://doi.org/10.1109/ectc.2011.5898657openalex-snapshot
Interposer design optimization for high frequency signal transmission in passive and active interposer using through silicon via (TSV)
inferredcites →https://doi.org/10.1109/ectc.2011.5898658openalex-snapshot
3-D Copper based TSV for 60-GHz applications
inferredcites →https://doi.org/10.1109/ectc.2011.5898660openalex-snapshot
Expert advisor for integrated virtual manufacturing and reliability for TSV/SiP based modules
inferredcites →https://doi.org/10.1109/ectc.2011.5898661openalex-snapshot
Thermo-mechanical behavior of through silicon vias in a 3D integrated package with inter-chip microbumps
inferredcites →https://doi.org/10.1109/ectc.2011.5898662openalex-snapshot
Wafer level warpage modeling methodology and characterization of TSV wafers
inferredcites →https://doi.org/10.1109/ectc.2011.5898663openalex-snapshot
A thermal performance measurement method for blind through silicon vias (TSVs) in a 300mm wafer
inferredcites →https://doi.org/10.1109/ectc.2011.5898675openalex-snapshot
Application of piezoresistive stress sensor in wafer bumping and drop impact test of embedded ultra thin device
inferredcites →https://doi.org/10.1109/ectc.2011.5898692openalex-snapshot
Implementation of an industry compliant, 5×50μm, via-middle TSV technology on 300mm wafers
inferredcites →https://doi.org/10.1109/ectc.2011.5898693openalex-snapshot
Impact of slurry in Cu CMP (chemical mechanical polishing) on Cu topography of Through Silicon Vias (TSVs), re-distribution layers, and Cu exposure
inferredcites →https://doi.org/10.1109/ectc.2011.5898694openalex-snapshot
Novel thinning/backside passivation for substrate coupling depression of 3D IC
inferredcites →https://doi.org/10.1109/ectc.2011.5898699openalex-snapshot
Design and reliability analysis of pyramidal shape 3-layer stacked TSV die package
inferredcites →https://doi.org/10.1109/ectc.2011.5898700openalex-snapshot
Interfacial reliability and micropartial stress analysis between TSV and CPB through NIT and MSA
inferredcites →https://doi.org/10.1109/ectc.2011.5898701openalex-snapshot
Electro- and thermomigration in micro bump interconnects for 3D integration
inferredcites →https://doi.org/10.1109/ectc.2011.5898704openalex-snapshot
Characterization and reliability assessment of solder microbumps and assembly for 3D IC integration
inferredcites →https://doi.org/10.1109/ectc.2011.5898705openalex-snapshot
Temperature-dependent thermal stress determination for through-silicon-vias (TSVs) by combining bending beam technique with finite element analysis
inferredcites →https://doi.org/10.1109/ectc.2011.5898723openalex-snapshot
Zero-level packaging for (RF-)MEMS implementing TSVs and metal bonding
inferredcites →https://doi.org/10.1109/ectc.2011.5898727openalex-snapshot
LED packaging using silicon substrate with cavities for phosphor printing and copper-filled TSVs for 3D interconnection
inferredcites →https://doi.org/10.1109/ectc.2011.5898734openalex-snapshot
Effect of blind hole depth and shape of solder joint on the reliability of through silicon via (TSV)
inferredcites →https://doi.org/10.1109/ectc.2011.5898748openalex-snapshot
Bumping and stacking processes for 3D IC using fluxfree polymer
inferredcites →https://doi.org/10.1109/ectc.2011.5898760openalex-snapshot
Integrated process for silicon wafer thinning
inferredcites →https://doi.org/10.1109/ectc.2011.5898761openalex-snapshot
Characterization of thermo-mechanical stress and reliability issues for Cu-filled TSVs
inferredcites →https://doi.org/10.1109/ectc.2011.5898767openalex-snapshot
Advanced wafer thinning and handling for through silicon via technology
inferredcites →https://doi.org/10.1109/ectc.2011.5898776openalex-snapshot
Evaluation of additives and current mode on copper via filling
inferredcites →https://doi.org/10.1109/ectc.2011.5898782openalex-snapshot
Novel chip stacking process for 3D integration
inferredcites →https://doi.org/10.1109/ectc.2011.5898788openalex-snapshot
Study on TSV with new filling method and alloy for advanced 3D-SiP
inferredcites →https://doi.org/10.1109/ectc.2011.5898790openalex-snapshot
Electrical, optical and fluidic through-silicon vias for silicon interposer applications
inferredcites →https://doi.org/10.1109/ectc.2011.5898797openalex-snapshot
Coupled electrical and thermal 3D IC centric microfluidic heat sink design and technology
inferredcites →https://doi.org/10.1109/ectc.2011.5898806openalex-snapshot
Advanced solder TSV filling technology developed with vacuum and wave soldering
inferredcites →https://doi.org/10.1109/eptc.2008.4763462openalex-snapshot
Process Development and Reliability of Microbumps
inferredcites →https://doi.org/10.1109/eptc.2008.4763465openalex-snapshot
Development of Fine Pitch Solder Microbumps for 3D Chip Stacking
inferredcites →https://doi.org/10.1109/eptc.2008.4763605openalex-snapshot
Evaluation of Stresses in Thin Device Wafer using Piezoresistive Stress Sensor
inferredcites →https://doi.org/10.1109/eptc.2008.4763607openalex-snapshot
C2W bonding method for MEMS applications
inferredcites →https://doi.org/10.1109/eptc.2009.5416440openalex-snapshot
3D integration of image sensor SiP using TSV silicon interposer
inferredcites →https://doi.org/10.1109/eptc.2009.5416445openalex-snapshot
Effect of TSV interposer on the thermal performance of FCBGA package
inferredcites →https://doi.org/10.1109/esime.2011.5765764openalex-snapshot
Energy release rate investigation for through silicon vias (TSVs) in 3D IC integration
inferredcites →https://doi.org/10.1109/icept.2009.5270759openalex-snapshot
Moiré method for nanoprecision wafer-to-wafer alignment: Theory, simulation and application
inferredcites →https://doi.org/10.1109/iedm.1986.191227openalex-snapshot
Concept and basic technologies for 3-D IC structure
inferredcites →https://doi.org/10.1109/iedm.2006.346785openalex-snapshot
Structure, Design and Process Control for Cu Bonded Interconnects in 3D Integrated Circuits
inferredcites →https://doi.org/10.1109/iedm.2008.4796762openalex-snapshot
A 300-mm wafer-level three-dimensional integration scheme using tungsten through-silicon via and hybrid Cu-adhesive bonding
inferredcites →https://doi.org/10.1109/iitc.2007.382392openalex-snapshot
Challenges for 3D IC integration: bonding quality and thermal management
inferredcites →https://doi.org/10.1109/isscc.2006.1696163openalex-snapshot
Laser Radar Imager Based on 3D Integration of Geiger-Mode Avalanche Photodiodes with Two SOI Timing Circuit Layers
inferredcites →https://doi.org/10.1109/jproc.1998.658762openalex-snapshot
Cramming More Components Onto Integrated Circuits
inferredcites →https://doi.org/10.1109/jproc.2008.2007464openalex-snapshot
System on Wafer: A New Silicon Concept in SiP
inferredcites →https://doi.org/10.1109/jssc.2006.877252openalex-snapshot
3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias
inferredcites →https://doi.org/10.1109/jssc.2009.2034408openalex-snapshot
8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology
inferredcites →https://doi.org/10.1109/jstqe.2009.2020812openalex-snapshot
Au–Au Surface-Activated Bonding and Its Application to Optical Microsensors With 3-D Structure
inferredcites →https://doi.org/10.1109/proc.1986.13686openalex-snapshot
Three-dimensional IC trends
inferredcites →https://doi.org/10.1109/smic.2009.4770536openalex-snapshot
Wafer-Scale 3D Integration of Silicon-on-Insulator RF Amplifiers
inferredcites →https://doi.org/10.1109/soi.2007.4357865openalex-snapshot
Scaling Three-Dimensional SOI Integrated-Circuit Technology
inferredcites →https://doi.org/10.1109/soi.2007.4357867openalex-snapshot
Thermal Effects of Three Dimensional Integrated Circuit Stacks
inferredcites →https://doi.org/10.1109/tadvp.2006.873138openalex-snapshot
Bumpless Interconnect Through Ultrafine Cu Electrodes by Means of Surface-Activated Bonding (SAB) Method
inferredcites →https://doi.org/10.1109/tadvp.2009.2021661openalex-snapshot
Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps
inferredcites →https://doi.org/10.1109/tcapt.2009.2012719openalex-snapshot
Fabrication of Silicon Carriers With TSV Electrical Interconnections and Embedded Thermal Solutions for High Power 3-D Packages
inferredcites →https://doi.org/10.1109/tcapt.2009.2033039openalex-snapshot
Integrated Liquid Cooling Systems for 3-D Stacked TSV Modules
inferredcites →https://doi.org/10.1109/tcapt.2009.2037608openalex-snapshot
Development of 3-D Silicon Module With TSV for System in Packaging
inferredcites →https://doi.org/10.1109/tcapt.2010.2046487openalex-snapshot
Process Development and Reliability of Microbumps
inferredcites →https://doi.org/10.1109/tcpmt.2010.2101911openalex-snapshot
Development of Large Die Fine-Pitch Cu/Low-$k$ FCBGA Package With Through Silicon via (TSV) Interposer
inferredcites →https://doi.org/10.1109/tcpmt.2012.2186297openalex-snapshot
3-D Packaging With Through-Silicon Via (TSV) for Electrical and Fluidic Interconnections
inferredcites →https://doi.org/10.1109/ted.2006.882043openalex-snapshot
A wafer-scale 3-D circuit integration technology
inferredcites →https://doi.org/10.1109/vlsic.2006.1705326openalex-snapshot
Through Silicon Via and 3-D Wafer/Chip Stacking Technology
inferredcites →https://doi.org/10.1109/vtsa.2008.4530815openalex-snapshot
Effects of Through-BOX Vias on SOI MOSFETs
inferredcites →https://doi.org/10.1115/1.2792229openalex-snapshot
Nonlinear Analysis of Full-Matrix and Perimeter Plastic Ball Grid Array Solder Joints
inferredcites →https://doi.org/10.1115/1.2792236openalex-snapshot
Thermal and Mechanical Evaluations of a Cost-Effective Plastic Ball Grid Array Package
inferredcites →https://doi.org/10.1115/1.2793847openalex-snapshot
Effect of Heat-Spreader Sizes on the Thermal Performance of Large Cavity-Down Plastic Ball Grid Array Packages
inferredcites →https://doi.org/10.1115/1.2905434openalex-snapshot
Solder Joint Reliability—Theory and Applications
inferredcites →https://doi.org/10.1115/1.4004861openalex-snapshot
Embedded Three-Dimensional Hybrid Integrated Circuit Integration System-in-Package With Through-Silicon Vias for Opto-Electronic Interconnects in Organic Substrates/Printed Circuit Boards
inferredcites →https://doi.org/10.1115/imece2010-37783openalex-snapshot
State-of-the-Art and Trends in Through-Silicon Via (TSV) and 3D Integrations
inferredcites →https://doi.org/10.1115/imece2010-40974openalex-snapshot
Embedded 3D Hybrid IC Integration System-in-Package (SiP) for Opto-Electronic Interconnects in Organic Substrates
inferredcites →https://doi.org/10.1115/imece2010-40975openalex-snapshot
Thermal-Enhanced and Cost-Effective 3D IC Integration With TSV (Through-Silicon Via) Interposers for High-Performance Applications
inferredcites →https://doi.org/10.1115/interpack2009-89380openalex-snapshot
Effects of TSV (Through Silicon Via) Interposer/Chip on the Thermal Performances of 3D IC Packaging
inferredcites →https://doi.org/10.1115/ipack2011-52205openalex-snapshot
Effects of TSV Interposer on the Reliability of 3D IC Integration SiP
inferredcites →https://doi.org/10.1117/12.764032openalex-snapshot
Design and analysis of 3D stacked optoelectronics on optical printed circuit boards
inferredcites →https://doi.org/10.1142/s0960313199000209openalex-snapshot
DESIGN, MANUFACTURING, AND TESTING OF A NOVEL PLASTIC BALL GRID ARRAY PACKAGE
inferredcites →https://doi.org/10.1147/jrd.2008.5388558openalex-snapshot
Fabrication and characterization of robust through-silicon vias for silicon-carrier applications
inferredcites →https://doi.org/10.1177/0954406211407256openalex-snapshot
Advanced MEMS Packaging
inferredcites →https://doi.org/10.1535/itj.1103.03openalex-snapshot
Package Technology to Address the Memory Bandwidth Challenge for Terascale Computing
inferredcites →https://doi.org/10.4071/001c.160717openalex-snapshot
Design and Process of 3D MEMS Packaging
inferredcites →https://doi.org/10.4071/1551-4897-7.1.10openalex-snapshot
Design and Process of 3D MEMS System-in-Package (SiP)
inferredcites →https://doi.org/10.4071/1551-4897-7.1.35openalex-snapshot
Critical Issues of TSV and 3D IC Integration
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All-2D electronics for AI processing
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Etch the borosilicate glass to form a straight through-glass-via based on the FLACE technology
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Fast and Accurate Machine Learning Compact Models for Interconnect Parasitic Capacitances Considering Systematic Process Variations
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Thermal evaluation and analyses of 3D IC integration SiP with TSVs for network system applications
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Low temperature solid-state-diffusion bonding for fine-pitch Cu/Sn/Cu interconnect
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3D heterogeneous integration structure based on 40 nm- and 0.18 µm-technology nodes
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Double-Densified Vertically Aligned Carbon Nanotube Bundles for Application in 3D Integration High Aspect Ratio TSV Interconnects
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Wet Etched Silicon Interposer for the 2.5D Stacking of CMOS and Optoelectronic Dies
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Study of Chip Stacking Process and Electrical Characteristic Evaluation of Cu Pillar Joint Between Chips Including TSV
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Board Level Reliability Optimization for 3D IC Packages with Extra Large Interposer
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Low Temperature and Pressureless Microfluidic Electroless Bonding Process for Vertical Interconnections
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Low-Temperature Chip Scale Cu-Cu Hybrid Bonding by Electroless Ag Passivation
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Novel Metrology For Experimentally Visualizing Cu-Cu Bonding Induced Thermal Stress
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Deep Reinforcement Learning-based Through Silicon Via (TSV) Array Design Optimization Method considering Crosstalk
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Electrical modelling of Through Silicon Vias (TSVs) and their impact on a CMOS circuit: Ring oscillator
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Intrinsic Stress Effect of Fabricated Processes on the Warpage and Microbump Reliability of Thin-Type 3D-ICs Packaging
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The effect of TSV design parameters on the manufacturability of TSV interposers
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Development of new TSV structure composing of intermetallic compounds
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Size and geometry effects on microstructural evolution in Sn microbumps during isothermal aging
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PhotoFourier: A Photonic Joint Transform Correlator-Based Neural Network Accelerator
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Computationally efficient standard-cell FEM-based thermal analysis
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TCAR: Thermal and Congestion-Aware Routing Algorithm in a Partially Connected 3D Network on Chip
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Analysis of Through Silicon Vias and substrate coupling in 3D CMOS circuits by Spice simulations
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Reliability studies on micro-joints for 3D-stacked chip
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Microstructural design in ultrafine interconnects under current stressing
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Low thermal resistance design for a 2.5D package
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Dry etching of fused silica glass in C4F8/Ar inductively coupled plasmas for through glass via (TGV) applications
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Reliability of TSV interconnects: Thermal shock and mechanical properties
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The modeling of DC current crowding for Through-silicon Via in 3-D IC
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Opening the hole of the backside silicon and forming the alloy bump for TSVs
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A simplification method of solder joints for thermal analysis in 3D packages
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A coupled thermal and mechanical modeling to investigate the stress of TSVs considering insulation layer
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A wet process to fabricate silicon oxide layer for through-silicon-via insulator application
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Research on Electrical Characteristics of Multi-chip Itegration for the Fifth-Generation Communication
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Effect of Interfacial Cracks between TSV and RDL on Electromigration Reliability
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Efficient Thermal Management Strategies for 3D-SiP Architectures
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Micro-masking removal of TSV and cavity during ICP etching using parameter control in 3D and MEMS integrations
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Controlling efficiency of laser drilling
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High density routing with electrical performance analysis using fine line package structure
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Polymer TSV fabrication scheme with its electrical and reliability test vehicle
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Simulation Analysis of Structure Design for Low Temperature Cu-Cu Direct Bonding in Heterogeneous Integration and Advanced Packaging Systems
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Fabrication and reliability investigation of copper pillar and tapered through silicon via (TSV) for direct bonding in 3D integration
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Comparative study of transmission lines design for 2.5D silicon interposer
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Analytical modeling and numerical simulations of temperature field in TSV-based 3D ICs
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Performance modeling and optimization for on-chip interconnects in 3D memory arrays
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STA compatible backend design flow for TSV-based 3-D ICs
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Testing and Fault-Localization Solutions for Monolithic 3D ICs
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Air cooling limits of 3D stacked logic processor and memory dies
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Research on the Design of a Novel Butterfly-Shaped Through-Silicon Via (TSV) Structure
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TSV Antennas for Multi-Band Wireless Communication
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3-D Integration and Through-Silicon Vias in MEMS and Microsensors
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A New Prewetting Process of Through Silicon Vias (TSV) Electroplating for 3D Integration
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Thermal-Aware Design Space Exploration of 3-D Systolic ML Accelerators
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Quantum-Modulated Poisson Encoders for Hybrid QPU Workloads: A Closed-Form Hardware-Selection Frontier for Edge Inference
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Enabling Continuous Cu Seed Layer for Deep Through-Silicon-Vias With High Aspect Ratio by Sequential Sputtering and Electroless Plating
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A versatile optical system for metrology and defects inspection of 3D integration processes
inferred← citeshttps://doi.org/10.1109/mixdes.2016.7529743openalex-snapshot
Coupled thermo-fluidic simulation for design space exploration of microchannels in liquid-cooled 3D ICs
inferred← citeshttps://doi.org/10.1109/mwscas.2017.8052879openalex-snapshot
Advertiser elevator: A fault tolerant routing algorithm for partially connected 3D Network-on-Chips
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Manufacturing pathway and experimental demonstration for nanoscale fine-grained 3-D integrated circuit fabric
inferred← citeshttps://doi.org/10.1109/nanoarch.2015.7180605openalex-snapshot
Architecting 3-D integrated circuit fabric with intrinsic thermal management features
inferred← citeshttps://doi.org/10.1109/pacet56979.2022.9976326openalex-snapshot
3D IC Design-for-Test with Implementation of the IEEE 1149.1-2013, the IEEE 1500-2005, and the IEEE 1838-2019 Standard
inferred← citeshttps://doi.org/10.1109/s3s.2017.8309205openalex-snapshot
New thermal management approach for transistor-level 3-D integtration
inferred← citeshttps://doi.org/10.1109/sapiw.2017.7944026openalex-snapshot
3D interconnect optimization for single channel 100-GBps transmission in a photonic interposer
inferred← citeshttps://doi.org/10.1109/tc.2015.2498550openalex-snapshot
Capacitive and Inductive TSV-to-TSV Resilient Approaches for 3D ICs
inferred← citeshttps://doi.org/10.1109/tcad.2015.2459044openalex-snapshot
A Distributed, Reconfigurable, and Reusable BIST Infrastructure for Test and Diagnosis of 3-D-Stacked ICs
inferred← citeshttps://doi.org/10.1109/tcad.2019.2917846openalex-snapshot
Addressing a New Class of Reliability Threats in 3-D Network-on-Chips
inferred← citeshttps://doi.org/10.1109/tcad.2021.3101145openalex-snapshot
Topological Structure and Physical Layout Co-Design for Wavelength-Routed Optical Networks-on-Chip
inferred← citeshttps://doi.org/10.1109/tcpmt.2012.2223758openalex-snapshot
Thermo-Mechanical Design Rules for the Fabrication of TSV Interposers
inferred← citeshttps://doi.org/10.1109/tcpmt.2014.2322907openalex-snapshot
Void Detection in TSVs With X-Ray Image Multithreshold Segmentation and Artificial Neural Networks
inferred← citeshttps://doi.org/10.1109/tcpmt.2014.2363191openalex-snapshot
Incapability of Drilling With a High-Power-Density Beam
inferred← citeshttps://doi.org/10.1109/tcpmt.2015.2418274openalex-snapshot
21-Layer 3-D Chip Stacking Based on Cu-Sn Bump Bonding
inferred← citeshttps://doi.org/10.1109/tcpmt.2015.2477075openalex-snapshot
Failure Analysis and Experimental Verification for Through-Silicon-via Underfill Dispensing on 3-D Chip Stack Package
inferred← citeshttps://doi.org/10.1109/tcpmt.2015.2511082openalex-snapshot
A Simulation Tool for Rapid Investigation of Trends in 3-DIC Performance and Power Consumption
inferred← citeshttps://doi.org/10.1109/tcpmt.2018.2839762openalex-snapshot
Fabrication and RF Property Evaluation of High-Resistivity Si Interposer for 2.5-D/3-D Heterogeneous Integration of RF Devices
inferred← citeshttps://doi.org/10.1109/tcpmt.2019.2896194openalex-snapshot
Study of Annular Copper-Filled TSVs of Sensor and Interposer Chips for 3-D Integration
inferred← citeshttps://doi.org/10.1109/tcpmt.2020.2994021openalex-snapshot
Phase-Field Study of Thermomigration in 3-D IC Micro Interconnects
inferred← citeshttps://doi.org/10.1109/tcpmt.2020.3047907openalex-snapshot
High-Aspect-Ratio TSV Process With Thermomigration Refilling of Au–Si Eutectic Alloy
inferred← citeshttps://doi.org/10.1109/tcpmt.2021.3068350openalex-snapshot
Grid-Based Redistribution Layers Within 3-D Power Networks
inferred← citeshttps://doi.org/10.1109/tcpmt.2024.3435863openalex-snapshot
Parametric Modeling of Coupled Stripline Coupler With Arbitrary Operating Frequency and Coupling Coefficient in Silicon-Based 3-D RF Integration
inferred← citeshttps://doi.org/10.1109/tcpmt.2024.3452637openalex-snapshot
Electrical–Thermal Co-Analysis of Through-Silicon Vias (TSVs) Integrated Within Micropin-Fin Heatsink for 3-D Heterogeneous Integration (HI)
inferred← citeshttps://doi.org/10.1109/tcpmt.2026.3695170openalex-snapshot
The In Situ Electrical Measurement of Hybrid Bonding
inferred← citeshttps://doi.org/10.1109/ted.2013.2243452openalex-snapshot
A Thermal Isolation Technique Using Through-Silicon Vias for Three-Dimensional ICs
inferred← citeshttps://doi.org/10.1109/ted.2023.3293780openalex-snapshot
A Modeling Study of Stacked Cu-CNT TSV on Electrical, Thermal, and Reliability Analysis
inferred← citeshttps://doi.org/10.1109/ted.2023.3297078openalex-snapshot
A Modeling Study on Electrical and Thermal Behavior of CNT TSV for Multilayer Structure
inferred← citeshttps://doi.org/10.1109/therminic.2014.6972486openalex-snapshot
Advancing the thermal stability of 3D-IC's using logi-thermal simulation
inferred← citeshttps://doi.org/10.1109/tpds.2023.3264698openalex-snapshot
An Efficient Algorithm for Hamiltonian Path Embedding of $k$-Ary $n$-Cubes under the Partitioned Edge Fault Model
inferred← citeshttps://doi.org/10.1109/tsm.2014.2309591openalex-snapshot
Rapidly Void Detection in TSVs With 2-D X-Ray Imaging and Artificial Neural Networks
inferred← citeshttps://doi.org/10.1109/tsm.2018.2805279openalex-snapshot
Fabrication and Characterization of Annular Copper Through-Silicon via for Passive Interposer Applications
inferred← citeshttps://doi.org/10.1109/tsm.2019.2946883openalex-snapshot
Crack-Free Fabrication and Electrical Characterization of Coaxial Ultra-Low-Resistivity-Silicon Through-Silicon-Vias
inferred← citeshttps://doi.org/10.1109/tvlsi.2016.2516520openalex-snapshot
2.31-Gb/s/ch Area-Efficient Crosstalk Canceled Hybrid Capacitive Coupling Interconnect for 3-D Integration
inferred← citeshttps://doi.org/10.1109/tvlsi.2021.3073070openalex-snapshot
High-Performance Logic-on-Memory Monolithic 3-D IC Designs for Arm Cortex-A Processors
inferred← citeshttps://doi.org/10.1117/12.2641690openalex-snapshot
Single-pass frame generation for multi-layer 3D circuits
inferred← citeshttps://doi.org/10.1117/12.3027317openalex-snapshot
Challenges and opportunities in non-destructive characterization of stacked IC packaging: insights from SAM and 3D x-ray analysis
inferred← citeshttps://doi.org/10.1117/12.3028177openalex-snapshot
Motivating automated multimodal failure analysis for heterogeneously integrated devices
inferred← citeshttps://doi.org/10.1145/2236576.2236579openalex-snapshot
Exploration of heuristic scheduling algorithms for 3D multicore processors
inferred← citeshttps://doi.org/10.1145/2401716.2401725openalex-snapshot
A high-efficiency low-cost heterogeneous 3D network-on-chip design
inferred← citeshttps://doi.org/10.1145/2966986.2967045openalex-snapshot
IC thermal analyzer for versatile 3-D structures using multigrid preconditioned krylov methods
inferred← citeshttps://doi.org/10.1145/3264736openalex-snapshot
System-Level Analysis of 3D ICs with Thermal TSVs
inferred← citeshttps://doi.org/10.1145/3340109openalex-snapshot
Energy Efficient Chip-to-Chip Wireless Interconnection for Heterogeneous Architectures
inferred← citeshttps://doi.org/10.1145/3372780.3378169openalex-snapshot
Full-Chip Electro-Thermal Coupling Extraction and Analysis for Face-to-Face Bonded 3D ICs
inferred← citeshttps://doi.org/10.1145/3473462openalex-snapshot
Design Automation and Test Solutions for Monolithic 3D ICs
inferred← citeshttps://doi.org/10.1360/n112016-00083openalex-snapshot
Micro/Nano-scale integrated circuits and new emerging hybrid integration techniques
inferred← citeshttps://doi.org/10.14445/23488549/ijece-v10i6p103openalex-snapshot
An Analog Circuit Designing Model via Machine Learning for Stage Classification and Evolutionary Solution Optimization Algorithm
inferred← citeshttps://doi.org/10.1587/elex.13.20162001openalex-snapshot
Chip-to-chip interconnect integration technologies
inferred← citeshttps://doi.org/10.23919/date51398.2021.9473921openalex-snapshot
Advances in Testing and Design-for-Test Solutions for M3D Integrated Circuits
inferred← citeshttps://doi.org/10.23919/date69613.2026.11539364openalex-snapshot
Architecture, Design and Technology Co-optimization for 3D ICs with Advanced BSPDN Considering Power & Thermal Integrity Impact
inferred← citeshttps://doi.org/10.23919/icep.2018.8374676openalex-snapshot
Bonding of copper pillars using electroless Au plating
inferred← citeshttps://doi.org/10.23919/icep.2019.8733511openalex-snapshot
Bonding of Copper Pillars Using Electroless Cu Plating
inferred← citeshttps://doi.org/10.23919/mixdes.2018.8436886openalex-snapshot
Thermal-aware Floorplanning Guidelines for 3D ICs with Integrated Microchannels
inferred← citeshttps://doi.org/10.25148/etd.fi12042309openalex-snapshot
Power and Thermal Aware Scheduling for Real-time Computing Systems
inferred← citeshttps://doi.org/10.32657/10220/48586openalex-snapshot
Design, fabrication, and characterization of three-dimensional embedded capacitor in through-silicon via
inferred← citeshttps://doi.org/10.32657/10356/160146openalex-snapshot
3D interconnects and multi-module integrated surface electrode ion trap for scalable quantum information processing
inferred← citeshttps://doi.org/10.32657/10356/61734openalex-snapshot
Through-silicon-via (TSV) design, fabrication and characterization for 3D IC applications
inferred← citeshttps://doi.org/10.32657/10356/67281openalex-snapshot
Development of 3D electro-optical integration based on silicon photonic TSV interposer
inferred← citeshttps://doi.org/10.3390/ma11020319openalex-snapshot
Bottom–Up Electrodeposition of Large-Scale Nanotwinned Copper within 3D Through Silicon Via
inferred← citeshttps://doi.org/10.3390/ma14185226openalex-snapshot
Stress Impact of the Annealing Procedure of Cu-Filled TSV Packaging on the Performance of Nano-Scaled MOSFETs Evaluated by an Analytical Solution and FEA-Based Submodeling Technique
inferred← citeshttps://doi.org/10.3390/ma6104707openalex-snapshot
Multiscale Microstructures and Microstructural Effects on the Reliability of Microbumps in Three-Dimensional Integration
inferred← citeshttps://doi.org/10.3390/mi14061151openalex-snapshot
Fabrication and Characterization of Thin Metal Films Deposited by Electroless Plating with Organic Additives for Electrical Circuits Applications
inferred← citeshttps://doi.org/10.3390/mi16090968openalex-snapshot
Overview of Thermal Management Solution for 3D Integrated Circuits Using Carbon-Nanotube-Based Silicon Through-Vias
inferred← citeshttps://doi.org/10.3390/mi9120644openalex-snapshot
Fabrication and Characteristics of SnAgCu Alloy Nanowires for Electrical Connection Application
inferred← citeshttps://doi.org/10.3390/su8020114openalex-snapshot
Technology Evaluation and Selection of 3DIC Integration Using a Three-Stage Fuzzy MCDM
inferred← citeshttps://doi.org/10.3788/aos252249openalex-snapshot
玻璃基共封装光学前沿技术及应用（特邀）
inferred← citeshttps://doi.org/10.4028/www.scientific.net/amm.302.3openalex-snapshot
Application of Pico-Second Laser on Low-K Wafer Dicing
inferred← citeshttps://doi.org/10.5104/jiepeng.5.75openalex-snapshot
Thermal Performance of 3D IC Package with Embedded TSVs
inferred← citeshttps://doi.org/10.5573/jsts.2015.15.3.356openalex-snapshot
Study on the Thermal Transient Response of TSV Considering the Effect of Electronic-Thermal Coupling
inferred← citeshttps://doi.org/10.6117/kmeps.2014.21.1.031openalex-snapshot
Numerical Analysis of Warpage and Reliability of Fan-out Wafer Level Package
inferred← citeshttps://doi.org/10.6117/kmeps.2014.21.4.091openalex-snapshot
Cu-Filling Behavior in TSV with Positions in Wafer Level
inferred← citeshttps://doi.org/10.70675/2d740a06z3c55z4316z9c14zd7f4734ba204openalex-snapshot
Développement de films minces à base de nanoparticules diélectriques et optimisatisation des conditions de dépôt pour fabriquer des condensateurs de découplage utilisés dans des assemblages à haute densité de modules électroniques
inferred← citeshttps://doi.org/10.70675/b249d951z9c87z41f5zbb6bz987c67dd4518openalex-snapshot
Apport de la technologie d’intégration 3D à forte densité d’interconnexions pour les capteurs d'images CMOS
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