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Interconnect-Aware Coherence Protocols for Chip Multiprocessors
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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Simics: A full system simulation platform
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A 2.2 W, 80 MHz superscalar RISC microprocessor
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Performance optimizations, implementation, and verification of the SGI Challenge multiprocessor
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The Thrifty Barrier: Energy-Aware Synchronization in Shared-Memory Multiprocessors
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Improving Multiple-CMP Systems Using Token Coherence
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Microarchitectural Wire Management for Performance and Power in Partitioned Architectures
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Power Efficient Processor Architecture and The Cell Processor
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The Soft Error Problem: An Architectural Perspective
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The SPLASH-2 programs: characterization and methodological considerations
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Dynamic self-invalidation: reducing coherence overhead in shared-memory multiprocessors
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Memory sharing predictor: the key to a speculative coherent DSM
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Clock rate versus IPC: the end of the road for conventional microarchitectures
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Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling
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Near speed-of-light signaling over on-chip electrical interconnects
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Parallel Computer Architecture: A Hardware/Software Approach
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TLC: transmission line caches
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Managing Wire Delay in Large Chip-Multiprocessor Caches
inferredcites →https://doi.org/10.1109/mm.2002.997878openalex-snapshot
Intel 870: a building block for cost-effective, scalable servers
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A power model for routers: modeling alpha 21364 and infiniband routers
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Niagara: A 32-Way Multithreaded Sparc Processor
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The use of prediction for accelerating upgrade misses in cc-NUMA multiprocessors
inferredcites →https://doi.org/10.1109/ted.2002.804706openalex-snapshot
A power-optimal repeater insertion methodology for global interconnects in nanometer designs
inferredcites →https://doi.org/10.1109/ted.2003.820651openalex-snapshot
A Global Interconnect Optimization Scheme for Nanometer Scale VLSI With Implications for Latency, Bandwidth, and Power Dissipation
inferredcites →https://doi.org/10.1145/1088149.1088154openalex-snapshot
A NUCA substrate for flexible CMP cache sharing
inferredcites →https://doi.org/10.1145/1105734.1105747openalex-snapshot
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
inferredcites →https://doi.org/10.1145/165123.165146openalex-snapshot
Adaptive cache coherency for detecting migratory shared data
inferredcites →https://doi.org/10.1145/173682.165147openalex-snapshot
An adaptive cache coherence protocol optimized for migratory sharing
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Selective, accurate, and timely self-invalidation using last-touch prediction
inferredcites →https://doi.org/10.1145/966747.966750openalex-snapshot
Interconnect-power dissipation in a microprocessor
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Alleviating Thermal Constraints While Maintaining Performance Via Silicon- Based On-chip Optical Interconnects
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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A High Efficient On-Chip Interconnection Network in SIMD CMPs
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Group-caching for NoC based multicore cache coherent systems
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An Energy-Efficient Reconfigurable NoC Architecture with RF-Interconnects
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An Adaptive Cache Coherence Protocol Optimized for Producer-Consumer Sharing
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Selective GPU caches to eliminate CPU-GPU HW cache coherence
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Design of directory based cache coherence protocol verification logic in CMPs around TACA
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Helia: Heterogeneous Interconnect for Low Resolution Cache Access in snoop-based chip multiprocessors
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An efficient test design for CMPs cache coherence
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Address Compression and Heterogeneous Interconnects for Energy-Efficient High-Performance in Tiled CMPs
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Hardware Implementation Study of the Deficit Table Egress Link Scheduling Algorithm
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PEPCP: A Power-Efficient Parallel Coherence Protocol for Large-Scale Network-on-Chip
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Comparing the latency performance of the DTable and DRR schedulers
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DiCo-CMP: Efficient cache coherency in tiled CMP architectures
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FLEXclusion: Balancing cache capacity and on-chip bandwidth via Flexible Exclusion
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A Test Design for Quick Determination of Incoherency in Chip Multiprocessors' Cache Realizing MOESI Protocol
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MASI: An eviction aware cache coherence protocol for CMPs
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A Protocol Independent Test Design for Quick Determination of Incoherency in CMPs' Cache
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Design of coherence verification unit for heterogeneous CMPs
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Design of coherence verification unit for CMPs realizing dragon protocol
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Leveraging 3D Technology for Improved Reliability
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Adaptive data compression for high-performance low-power on-chip networks
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Power reduction of CMP communication networks via RF-interconnects
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Leveraging Wire Properties at the Microarchitecture Level
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Invalidate or Update? Revisiting Coherence for Tomorrow's Cache Hierarchies
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Energy-Efficient Hardware Prefetching for CMPs Using Heterogeneous Interconnects
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Using Heterogeneous Networks to Improve Energy Efficiency in Direct Coherence Protocols for Many-Core CMPs
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Heterogeneous Interconnects for Energy-Efficient Message Management in CMPs
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Designing a Physical Locality Aware Coherence Protocol for Chip-Multiprocessors
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A Framework to Provide Quality of Service over Advanced Switching
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Providing QoS with the Deficit Table Scheduler
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A Direct Coherence Protocol for Many-Core Chip Multiprocessors
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Balancing Performance and Cost in CMP Interconnection Networks
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81.6 GOPS Object Recognition Processor Based on a Memory-Centric NoC
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Interconnect design considerations for large NUCA caches
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Interconnect design considerations for large NUCA caches
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A consistency architecture for hierarchical shared caches
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An analysis of on-chip interconnection networks for large-scale chip multiprocessors
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Proximity coherence for chip multiprocessors
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Energy- and Performance-Efficient Communication Framework for Embedded MPSoCs through Application-Driven Release Consistency
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An adaptive cache coherence protocol for chip multiprocessors
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An optimized multicore cache coherence design for exploiting communication locality
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A hybrid NoC design for cache coherence optimization for chip multiprocessors
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Multi-Core Cache Hierarchies
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A case of area- and energy-efficient heterogeneous mesh network-on-chip
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Improving prefetching mechanisms for tiled CMP platforms
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