On the public citation graph
Leveraging 3D Technology for Improved Reliability
0 signed · 59 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/aspdac.2006.1594713openalex-snapshot
An automated design flow for 3d microarchitecture evaluation
inferredcites →https://doi.org/10.1109/dsn.2004.1311877openalex-snapshot
Characterizing the effects of transient faults on a high-performance processor pipeline
inferredcites →https://doi.org/10.1109/ftcs.1999.781037openalex-snapshot
AR-SMT: a microarchitectural approach to fault tolerance in microprocessors
inferredcites →https://doi.org/10.1109/hpca.2002.995696openalex-snapshot
Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling
inferredcites →https://doi.org/10.1109/hpca.2005.37openalex-snapshot
The Soft Error Problem: An Architectural Perspective
inferredcites →https://doi.org/10.1109/iccd.2005.65openalex-snapshot
Implementing caches in a 3D technology for high performance processors
inferredcites →https://doi.org/10.1109/icicdt.2005.1502578openalex-snapshot
Design aspects of a microprocessor data cache using 3D die interconnect technology
inferredcites →https://doi.org/10.1109/isca.2000.854380openalex-snapshot
Wattch: a framework for architectural-level power analysis and optimizations
inferredcites →https://doi.org/10.1109/isca.2006.23openalex-snapshot
Interconnect-Aware Coherence Protocols for Chip Multiprocessors
inferredcites →https://doi.org/10.1109/mdt.2005.134openalex-snapshot
Bridging the Processor-Memory Performance Gapwith 3D IC Technology
inferredcites →https://doi.org/10.1109/micro.1999.809458openalex-snapshot
DIVA: a reliable substrate for deep submicron microarchitecture design
inferredcites →https://doi.org/10.1109/micro.2002.1176258openalex-snapshot
Orion: a power-performance simulator for interconnection networks
inferredcites →https://doi.org/10.1109/micro.2002.1176261openalex-snapshot
Optimizing pipelines for power and performance
inferredcites →https://doi.org/10.1109/micro.2003.1253179openalex-snapshot
Razor: a low-power pipeline based on circuit-level timing speculation
inferredcites →https://doi.org/10.1109/micro.2003.1253185openalex-snapshot
Single-ISA heterogeneous multi-core architectures: the potential for processor power reduction
inferredcites →https://doi.org/10.1109/micro.2006.18openalex-snapshot
Die Stacking (3D) Microarchitecture
inferredcites →https://doi.org/10.1109/mm.2005.34openalex-snapshot
Montecito: A Dual-Core, Dual-Thread Itanium Processor
inferredcites →https://doi.org/10.1109/relphy.2006.251220openalex-snapshot
Radiation-Induced Soft Error Rates of Advanced CMOS Bulk Devices
inferredcites →https://doi.org/10.1109/tpds.2007.1090openalex-snapshot
Power Efficient Approaches to Redundant Multithreading
inferredcites →https://doi.org/10.1145/1105734.1105739openalex-snapshot
Exploring the cache design space for large scale CMPs
inferredcites →https://doi.org/10.1145/1127908.1127915openalex-snapshot
Thermal analysis of a 3D die-stacked high-performance microprocessor
inferredcites →https://doi.org/10.1145/1146909.1147160openalex-snapshot
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy
inferredcites →https://doi.org/10.1145/1148015.1148016openalex-snapshot
Design space exploration for 3D architectures
inferredcites →https://doi.org/10.1145/1150019.1136497openalex-snapshot
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
inferredcites →https://doi.org/10.1145/1250662.1250708openalex-snapshot
Interconnect design considerations for large NUCA caches
inferredcites →https://doi.org/10.1145/339647.339652openalex-snapshot
Transient fault detection via simultaneous multithreading
inferredcites →https://doi.org/10.1145/605397.605403openalex-snapshot
Automatically characterizing large scale program behavior
inferredcites →https://doi.org/10.1145/775832.775920openalex-snapshot
Parameter variations and impact on circuits and microarchitecture
inferredcites →https://doi.org/10.1145/859618.859620openalex-snapshot
Temperature-aware microarchitecture
inferredcites →https://doi.org/10.1145/859618.859631openalex-snapshot
Transient-fault recovery for chip multiprocessors
inferredcites →https://doi.org/10.1145/981066.981091openalex-snapshot
Technology, performance, and computer-aided design of three-dimensional integrated circuits
inferredcites →https://doi.org/10.5555/563998.564027openalex-snapshot
Dual use of superscalar datapath for transient-fault detection and recovery
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-1-4419-0784-4_7openalex-snapshot
Three-Dimensional Microprocessor Design
inferred← citeshttps://doi.org/10.1007/978-3-642-23400-2_28openalex-snapshot
Token3D: Reducing Temperature in 3D Die-Stacked CMPs through Cycle-Level Power Control Mechanisms
inferred← citeshttps://doi.org/10.1016/j.jcss.2012.09.004openalex-snapshot
Developing a power-efficient and low-cost 3D NoC using smart GALS-based vertical channels
inferred← citeshttps://doi.org/10.1109/3dic.2013.6702316openalex-snapshot
The monolithic 3D advantage: Monolithic 3D is far more than just an alternative to 0.7x scaling
inferred← citeshttps://doi.org/10.1109/3dic.2014.7152172openalex-snapshot
Leveraging 3D-IC for on-chip timing uncertainty measurements
inferred← citeshttps://doi.org/10.1109/cit.2010.461openalex-snapshot
Distributed On-Chip Operating System for Network on Chip
inferred← citeshttps://doi.org/10.1109/coolchips.2011.5890921openalex-snapshot
COOL interconnect low power interconnection technology for scalable 3D LSI design
inferred← citeshttps://doi.org/10.1109/hpca.2010.5416628openalex-snapshot
An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidth
inferred← citeshttps://doi.org/10.1109/ipdpsw.2010.5470910openalex-snapshot
T-NUCA - a novel approach to non-uniform access latency cache architectures for 3D CMPs
inferred← citeshttps://doi.org/10.1109/isca.2008.13openalex-snapshot
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
inferred← citeshttps://doi.org/10.1109/isca.2008.15openalex-snapshot
3D-Stacked Memory Architectures for Multi-core Processors
inferred← citeshttps://doi.org/10.1109/isqed.2013.6523582openalex-snapshot
Hetero2 3D integration: A scheme for optimizing efficiency/cost of Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/jproc.2022.3218057openalex-snapshot
Technology Prospects for Data-Intensive Computing
inferred← citeshttps://doi.org/10.1109/mm.2016.53openalex-snapshot
Exploiting Interposer Technologies to Disintegrate and Reintegrate Multicore Processors
inferred← citeshttps://doi.org/10.1109/norchip.2010.5669453openalex-snapshot
Research and practices on 3D networks-on-chip architectures
inferred← citeshttps://doi.org/10.1109/optim.2012.6231859openalex-snapshot
Is 3D integration the way to future dependable computing platforms?
inferred← citeshttps://doi.org/10.1109/tetc.2019.2946887openalex-snapshot
Performance and Area Trade-Off of 3D-Stacked DRAM Based Chip Multiprocessor with Hybrid Interconnect
inferred← citeshttps://doi.org/10.1109/tmscs.2016.2550460openalex-snapshot
Security and Vulnerability Implications of 3D ICs
inferred← citeshttps://doi.org/10.1109/tpds.2015.2426179openalex-snapshot
A Survey of Techniques for Modeling and Improving Reliability of Computing Systems
inferred← citeshttps://doi.org/10.1109/tpds.2017.2780173openalex-snapshot
AROMa: Aging-Aware Deadlock-Free Adaptive Routing Algorithm and Online Monitoring in 3D NoCs
inferred← citeshttps://doi.org/10.1145/1394608.1382159openalex-snapshot
3D-Stacked Memory Architectures for Multi-core Processors
inferred← citeshttps://doi.org/10.1145/2765491.2765514openalex-snapshot
Zero-performance-overhead online fault detection and diagnosis in 3D stacked integrated circuits
inferred← citeshttps://doi.org/10.23919/date.2017.7927006openalex-snapshot
3DFAR: A three-dimensional fabric for reliable multi-core processors
inferred← citeshttps://doi.org/10.3390/technologies10010009openalex-snapshot
3D Scanning/Printing: A Technological Stride in Sculpture
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.