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Learning-Based SMT Processor Resource Distribution via Hill-Climbing
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-48311-x_101openalex-snapshot
A Study of a Simultaneous Multithreaded Processor Implementation
inferredcites →https://doi.org/10.1109/hpca.2003.1183522openalex-snapshot
Front-end policies for improved issue efficiency in SMT processors
inferredcites →https://doi.org/10.1109/ipdps.2001.924929openalex-snapshot
Boosting SMT performance by speculation control
inferredcites →https://doi.org/10.1109/micro.2001.991129openalex-snapshot
Handling long-latency loads in a simultaneous multithreading processor
inferredcites →https://doi.org/10.1109/micro.2004.17openalex-snapshot
Dynamically Controlled Resource Allocation in SMT Processors
inferredcites →https://doi.org/10.1109/mm.2003.1196115openalex-snapshot
Hyperthreading technology in the netburst microarchitecture
inferredcites →https://doi.org/10.1109/mm.2004.1289290openalex-snapshot
IBM power5 chip: a dual-core multithreaded processor
inferredcites →https://doi.org/10.1109/pact.2001.953283openalex-snapshot
Basic block distribution analysis to find periodic behavior and simulation points in applications
inferredcites →https://doi.org/10.1109/pact.2002.1105971openalex-snapshot
Transparent threads: resource sharing in SMT processors for high single-thread performance
inferredcites →https://doi.org/10.1109/pact.2003.1237998openalex-snapshot
The impact of resource partitioning on SMT processors
inferredcites →https://doi.org/10.1145/1006209.1006254openalex-snapshot
Back-end assignment schemes for clustered multithreaded processors
inferredcites →https://doi.org/10.1145/268806.268810openalex-snapshot
The SimpleScalar tool set, version 2.0
inferredcites →https://doi.org/10.1145/511399.511343openalex-snapshot
Symbiotic jobscheduling with priorities for a simultaneous multithreading processor
inferredcites →https://doi.org/10.1145/605397.605403openalex-snapshot
Automatically characterizing large scale program behavior
inferredcites →https://doi.org/10.1145/605397.605415openalex-snapshot
Design and evaluation of compiler algorithms for pre-execution
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-319-07518-1_12openalex-snapshot
History-Based Predictive Instruction Window Weighting for SMT Processors
inferred← citeshttps://doi.org/10.1109/candar51075.2020.00011openalex-snapshot
A Learning-based Fetch Thread Gating Mechanism for A Simultaneous Multithreading Processor
inferred← citeshttps://doi.org/10.1109/ccece.2017.7946728openalex-snapshot
On on-chip intelligence paradigms
inferred← citeshttps://doi.org/10.1109/hpca.2007.346201openalex-snapshot
A Memory-Level Parallelism Aware Fetch Policy for SMT Processors
inferred← citeshttps://doi.org/10.1109/hpca.2008.4658635openalex-snapshot
Runahead Threads to improve SMT performance
inferred← citeshttps://doi.org/10.1109/hpca.2015.7056026openalex-snapshot
XChange: A market-based approach to scalable dynamic multi-resource allocation in multicore architectures
inferred← citeshttps://doi.org/10.1109/ipdpsw.2010.5470909openalex-snapshot
Dynamic core partitioning for energy efficiency
inferred← citeshttps://doi.org/10.1109/isca.2016.29openalex-snapshot
Warped-Slicer: Efficient Intra-SM Slicing through Dynamic Resource Partitioning for GPU Multiprogramming
inferred← citeshttps://doi.org/10.1109/micro.2008.4771801openalex-snapshot
Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approach
inferred← citeshttps://doi.org/10.1109/mm.2024.3408719openalex-snapshot
Practical Online Reinforcement Learning for Microprocessors With Micro-Armed Bandit
inferred← citeshttps://doi.org/10.1109/pact.2013.6618810openalex-snapshot
An empirical model for predicting cross-core performance interference on multicore processors
inferred← citeshttps://doi.org/10.1109/sbac-pad.2008.17openalex-snapshot
Selection of the Register File Size and the Resource Allocation Policy on SMT Processors
inferred← citeshttps://doi.org/10.1109/tcad.2022.3197980openalex-snapshot
Amphis: Managing Reconfigurable Processor Architectures With Generative Adversarial Learning
inferred← citeshttps://doi.org/10.1109/tcad.2025.3537975openalex-snapshot
DynMap: A Heuristic Dynamic Mapper for CGRA Multitask Dynamic Resource Allocation
inferred← citeshttps://doi.org/10.1109/tpds.2010.199openalex-snapshot
Utilization-Based Resource Partitioning for Power-Performance Efficiency in SMT Processors
inferred← citeshttps://doi.org/10.1109/ubmk52708.2021.9559021openalex-snapshot
Fine-Tuning Throughput and QoS on SMT Cores
inferred← citeshttps://doi.org/10.1109/ubmk59864.2023.10286669openalex-snapshot
GQoSMT: On Guaranteeing the Quality of Service Requirements of Simultaneous Multithreading Processors
inferred← citeshttps://doi.org/10.1145/1274971.1274992openalex-snapshot
An L2-miss-driven early register deallocation for SMT processors
inferred← citeshttps://doi.org/10.1145/1454115.1454148openalex-snapshot
An adaptive resource partitioning algorithm for SMT processors
inferred← citeshttps://doi.org/10.1145/1455650.1455652openalex-snapshot
Reducing register pressure in SMT processors through L2-miss-driven early register release
inferred← citeshttps://doi.org/10.1145/1482619.1482620openalex-snapshot
Hill-climbing SMT processor resource distribution
inferred← citeshttps://doi.org/10.1145/1508244.1508260openalex-snapshot
Per-thread cycle accounting in SMT processors
inferred← citeshttps://doi.org/10.1145/1508284.1508260openalex-snapshot
Per-thread cycle accounting in SMT processors
inferred← citeshttps://doi.org/10.1145/1509864.1509867openalex-snapshot
Memory-level parallelism aware fetch policies for simultaneous multithreading processors
inferred← citeshttps://doi.org/10.1145/1735970.1736033openalex-snapshot
Probabilistic job symbiosis modeling for SMT processor scheduling
inferred← citeshttps://doi.org/10.1145/1735971.1736033openalex-snapshot
Probabilistic job symbiosis modeling for SMT processor scheduling
inferred← citeshttps://doi.org/10.1145/1736020.1736033openalex-snapshot
Probabilistic job symbiosis modeling for SMT processor scheduling
inferred← citeshttps://doi.org/10.1145/1815961.1815992openalex-snapshot
Dynamic warp subdivision for integrated branch and memory divergence tolerance
inferred← citeshttps://doi.org/10.1145/1816038.1815992openalex-snapshot
Dynamic warp subdivision for integrated branch and memory divergence tolerance
inferred← citeshttps://doi.org/10.1145/1854273.1854284openalex-snapshot
Dynamically managed multithreaded reconfigurable architectures for chip multiprocessors
inferred← citeshttps://doi.org/10.1145/1995896.1995927openalex-snapshot
Predictive coordination of multiple on-chip resources for chip multiprocessors
inferred← citeshttps://doi.org/10.1145/2019608.2019611openalex-snapshot
Managing SMT resource usage through speculative instruction window weighting
inferred← citeshttps://doi.org/10.1145/2207222.2207223openalex-snapshot
Probabilistic modeling for job symbiosis scheduling on SMT processors
inferred← citeshttps://doi.org/10.1145/2228360.2228409openalex-snapshot
Self-aware computing in the Angstrom processor
inferred← citeshttps://doi.org/10.1145/2528521.1508260openalex-snapshot
Per-thread cycle accounting in SMT processors
inferred← citeshttps://doi.org/10.1145/2541228.2541238openalex-snapshot
Dynamic microarchitectural adaptation using machine learning
inferred← citeshttps://doi.org/10.1145/2847254openalex-snapshot
Symmetry-Agnostic Coordinated Management of the Memory Hierarchy in Multicore Systems
inferred← citeshttps://doi.org/10.1145/3307650.3326633openalex-snapshot
Generative and multi-phase learning for computer systems optimization
inferred← citeshttps://doi.org/10.1145/3613424.3623780openalex-snapshot
Micro-Armed Bandit: Lightweight & Reusable Reinforcement Learning for Microarchitecture Decision-Making
inferred← citeshttps://doi.org/10.3906/elk-2005-50openalex-snapshot
Dynamic issue queue capping for simultaneous multithreaded processors
inferred← citeshttps://doi.org/10.4018/978-1-7998-7156-9.ch004openalex-snapshot
Intelligent Management of Mobile Systems Through Computational Self-Awareness
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