On the public citation graph
Memory Model = Instruction Reordering + Store Atomicity
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Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-48683-6_27openalex-snapshot
Verifying Sequential Consistency on Shared-Memory Multiprocessor Systems
inferredcites →https://doi.org/10.1109/2.546611openalex-snapshot
Shared memory consistency models: a tutorial
inferredcites →https://doi.org/10.1109/2.707614openalex-snapshot
Multiprocessors should support simple memory consistency models
inferredcites →https://doi.org/10.1109/isca.1990.134502openalex-snapshot
Weak ordering-a new definition
inferredcites →https://doi.org/10.1109/isca.1990.134503openalex-snapshot
Memory consistency and event ordering in scalable shared-memory multiprocessors
inferredcites →https://doi.org/10.1109/isca.1992.753300openalex-snapshot
Lazy Release Consistency for Software Distributed Shared Memory
inferredcites →https://doi.org/10.1109/isca.1993.698569openalex-snapshot
Transactional Memory: Architectural Support For Lock-free Data Structures
inferredcites →https://doi.org/10.1109/isca.1999.765947openalex-snapshot
Commit-Reconcile and Fences (CRF): a new memory model for architects and compiler writers
inferredcites →https://doi.org/10.1109/lics.1996.561322openalex-snapshot
Model-checking of correctness conditions for concurrent objects
inferredcites →https://doi.org/10.1109/memcod.2005.1487915openalex-snapshot
On the decidability of shared memory consistency veri~cation
inferredcites →https://doi.org/10.1109/micro.2001.991130openalex-snapshot
Correctly implementing value prediction in microprocessors that support multithreading or multiprocessing
inferredcites →https://doi.org/10.1109/opnarc.2003.1196379openalex-snapshot
Transparent and scalable client-side server selection using Netlets
inferredcites →https://doi.org/10.1109/tc.1979.1675439openalex-snapshot
How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs
inferredcites →https://doi.org/10.1109/tpds.2003.1225053openalex-snapshot
Verifying sequential consistency on shared-memory multiprocessors by model checking
inferredcites →https://doi.org/10.1145/277651.277690openalex-snapshot
Computation-centric memory models
inferredcites →https://doi.org/10.1145/353171.353172openalex-snapshot
Improving the Java memory model using CRF
inferredcites →https://doi.org/10.1145/378580.378604openalex-snapshot
Automatable verification of sequential consistency
inferredcites →https://doi.org/10.1145/42190.42277openalex-snapshot
Efficient and correct execution of parallel programs that share memory
inferredcites →https://doi.org/10.1145/777412.777467openalex-snapshot
Toward a decidable notion of sequential consistency
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/11947950_7openalex-snapshot
Programmer-Centric Conditions for Itanium Memory Consistency
inferred← citeshttps://doi.org/10.1007/978-3-319-98116-1_9openalex-snapshot
Test Generation and Lightweight Checking for Multi-core Memory Consistency
inferred← citeshttps://doi.org/10.1109/dsd.2012.27openalex-snapshot
Architecture Support and Comparison of Three Memory Consistency Models in NoC Based Systems
inferred← citeshttps://doi.org/10.1109/icpp.2009.54openalex-snapshot
Investigating High Performance RMA Interfaces for the MPI-3 Standard
inferred← citeshttps://doi.org/10.1109/isca45697.2020.00060openalex-snapshot
Relaxed Persist Ordering Using Strand Persistency
inferred← citeshttps://doi.org/10.1109/isca66397.2026.00156openalex-snapshot
QED: Scalable Consistency Verification of Memory Instruction Reordering in Hardware
inferred← citeshttps://doi.org/10.1109/micro50266.2020.00053openalex-snapshot
Speculative Enforcement of Store Atomicity
inferred← citeshttps://doi.org/10.1109/mm.2010.99openalex-snapshot
Address Translation Aware Memory Consistency
inferred← citeshttps://doi.org/10.1109/pact.2011.69openalex-snapshot
Modeling and Performance Evaluation of TSO-Preserving Binary Optimization
inferred← citeshttps://doi.org/10.1109/pact.2015.18openalex-snapshot
Parallel Methods for Verifying the Consistency of Weakly-Ordered Architectures
inferred← citeshttps://doi.org/10.1109/pact.2017.29openalex-snapshot
Weak Memory Models: Balancing Definitional Simplicity and Implementation Flexibility
inferred← citeshttps://doi.org/10.1109/tc.2011.41openalex-snapshot
Linear Time Memory Consistency Verification
inferred← citeshttps://doi.org/10.1145/1168857.1168865openalex-snapshot
A regulated transitive reduction (RTR) for longer memory race recording
inferred← citeshttps://doi.org/10.1145/1168917.1168865openalex-snapshot
A regulated transitive reduction (RTR) for longer memory race recording
inferred← citeshttps://doi.org/10.1145/1168918.1168865openalex-snapshot
A regulated transitive reduction (RTR) for longer memory race recording
inferred← citeshttps://doi.org/10.1145/1168919.1168865openalex-snapshot
A regulated transitive reduction (RTR) for longer memory race recording
inferred← citeshttps://doi.org/10.1145/1735970.1736057openalex-snapshot
Specifying and dynamically verifying address translation-aware memory consistency
inferred← citeshttps://doi.org/10.1145/1735971.1736057openalex-snapshot
Specifying and dynamically verifying address translation-aware memory consistency
inferred← citeshttps://doi.org/10.1145/1736020.1736057openalex-snapshot
Specifying and dynamically verifying address translation-aware memory consistency
inferred← citeshttps://doi.org/10.1145/1988915.1988917openalex-snapshot
There is nothing wrong with out-of-thin-air
inferred← citeshttps://doi.org/10.1145/1993806.1993819openalex-snapshot
The impact of memory models on software reliability in multiprocessors
inferred← citeshttps://doi.org/10.1145/2024724.2024842openalex-snapshot
Litmus tests for comparing memory consistency models
inferred← citeshttps://doi.org/10.1145/2445572.2445573openalex-snapshot
Deterministic Replay Using Global Clock
inferred← citeshttps://doi.org/10.1145/2485922.2485940openalex-snapshot
Exploring memory consistency for massively-threaded throughput-oriented processors
inferred← citeshttps://doi.org/10.1145/2508148.2485940openalex-snapshot
Exploring memory consistency for massively-threaded throughput-oriented processors
inferred← citeshttps://doi.org/10.1145/3009837.3009839openalex-snapshot
Mixed-size concurrency: ARM, POWER, C/C++11, and SC
inferred← citeshttps://doi.org/10.1145/3093333.3009839openalex-snapshot
Mixed-size concurrency: ARM, POWER, C/C++11, and SC
inferred← citeshttps://doi.org/10.1145/3314221.3314624openalex-snapshot
Promising-ARM/RISC-V: a simpler and faster operational concurrency model
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