On the public citation graph
Programmer-Centric Conditions for Itanium Memory Consistency
0 signed · 25 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/11864219_12openalex-snapshot
Capturing Register and Control Dependence in Memory Consistency Models with Applications to the Itanium Architecture
inferredcites →https://doi.org/10.1007/11947950_7openalex-snapshot
Programmer-Centric Conditions for Itanium Memory Consistency
inferredcites →https://doi.org/10.1007/978-3-540-27813-9_31openalex-snapshot
QB or Not QB: An Efficient Execution Verification Tool for Memory Orderings
inferredcites →https://doi.org/10.1007/978-3-540-39724-3_9openalex-snapshot
Analyzing the Intel Itanium Memory Ordering Rules Using Logic Programming and SAT
inferredcites →https://doi.org/10.1023/a:1022969405325openalex-snapshot
Checking Cache-Coherence Protocols with TLA+
inferredcites →https://doi.org/10.1109/2.546611openalex-snapshot
Shared memory consistency models: a tutorial
inferredcites →https://doi.org/10.1109/ipdps.2004.1302944openalex-snapshot
Nemos: a framework for axiomatic and executable specifications of memory consistency models
inferredcites →https://doi.org/10.1109/isca.2006.26openalex-snapshot
Memory Model = Instruction Reordering + Store Atomicity
inferredcites →https://doi.org/10.1109/tpds.2003.1199067openalex-snapshot
Information-flow models for shared memory with an application to the powerPC architecture
inferredcites →https://doi.org/10.1145/1148109.1148138openalex-snapshot
Translating between itanium and sparc memory consistency models
inferredcites →https://doi.org/10.1145/1150019.1136489openalex-snapshot
Memory Model = Instruction Reordering + Store Atomicity
inferredcites →https://doi.org/10.1145/1189736.1189737openalex-snapshot
Specifying memory consistency of write buffer multiprocessors
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/11864219_12openalex-snapshot
Capturing Register and Control Dependence in Memory Consistency Models with Applications to the Itanium Architecture
inferred← citeshttps://doi.org/10.1016/j.entcs.2007.04.007openalex-snapshot
What is Itanium Memory Consistency from the Programmer's Point of View?
inferred← citeshttps://doi.org/10.1145/1480881.1480929openalex-snapshot
The semantics of x86-CC multiprocessor machine code
inferred← citeshttps://doi.org/10.1145/1481839.1481842openalex-snapshot
The semantics of power and ARM multiprocessor machine code
inferred← citeshttps://doi.org/10.1145/1594834.1480929openalex-snapshot
The semantics of x86-CC multiprocessor machine code
inferred← citeshttps://doi.org/10.1145/3009837.3009839openalex-snapshot
Mixed-size concurrency: ARM, POWER, C/C++11, and SC
inferred← citeshttps://doi.org/10.1145/3093333.3009839openalex-snapshot
Mixed-size concurrency: ARM, POWER, C/C++11, and SC
inferred← citeshttps://doi.org/10.11575/prism/11978openalex-snapshot
Formal Models and Implementations of Distributed Shared Memory
inferred← citeshttps://doi.org/10.48550/arxiv.1306.0077openalex-snapshot
Partition Consistency: A Case Study in Modeling Systems with Weak Memory Consistency and Proving Correctness of their Implementations
inferred← citeshttps://doi.org/10.70675/6f86083bz89aez4751zb868zc4ee47a9ccc8openalex-snapshot
Vérification par model-checking de programmes concurrents paramétrés sur des modèles mémoires faibles
showing the first 12 of 13 · page through all 13
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.