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The BlackWidow High-Radix Clos Network
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Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1002/j.1538-7305.1953.tb01433.xopenalex-snapshot
A Study of Non-Blocking Switching Networks
inferredcites →https://doi.org/10.1006/jpdc.1996.0033openalex-snapshot
The Network Architecture of the Connection Machine CM-5
inferredcites →https://doi.org/10.1016/0376-5075(79)90032-1openalex-snapshot
Virtual cut-through: A new computer communication switching technique
inferredcites →https://doi.org/10.1109/12.53599openalex-snapshot
Performance analysis of k-ary n-cube interconnection networks
inferredcites →https://doi.org/10.1109/cmpeur.1989.93344openalex-snapshot
Mappable peripheral memory for high speed applications
inferredcites →https://doi.org/10.1109/his.2001.946702openalex-snapshot
The Alpha 21364 network architecture
inferredcites →https://doi.org/10.1109/isca.2005.35openalex-snapshot
Microarchitecture of a High-Radix Router
inferredcites →https://doi.org/10.1109/tc.1985.6312192openalex-snapshot
Fat-trees: Universal networks for hardware-efficient supercomputing
inferredcites →https://doi.org/10.1109/tc.1987.1676939openalex-snapshot
Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
inferredcites →https://doi.org/10.1109/tcom.1987.1096719openalex-snapshot
Input Versus Output Queueing on a Space-Division Packet Switch
inferredcites →https://doi.org/10.1145/139669.140384openalex-snapshot
The turn model for adaptive routing
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-030-78713-4_1openalex-snapshot
Microarchitecture of a Configurable High-Radix Router for the Post-Moore Era
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Megafly: A Topology for Exascale Systems
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A Learning-Based Approach to the Automated Design of MPSoC Networks
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A HoL-blocking aware mechanism for selecting the upward path in fat-tree topologies
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A fault-tolerant routing algorithm in HyperX topology based on unsafety vectors
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2-Dilated flattened butterfly: A nonblocking switching topology for high-radix networks
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Reducing complexity in tree-like computer interconnection networks
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Scaledmatx One : A Bundled-Data GALS Inference ASIC
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Sensitivity Analysis of Biomolecular Simulations using Symbolic Models
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Back-Track Routing for Fat-Tree Based Data Center Networks
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Comparing Global Link Arrangements for Dragonfly Networks
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A low hop distance hierarchical interconnection network
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Extended complete switch as ideal system network
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Enhancing Butterfly Fat Tree NoCs for FPGAs with Lightweight Flow Control
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New Link Arrangements for Dragonfly Networks
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HPP Switch: A Novel High Performance Switch for HPC
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The Impact of Optics on HPC System Interconnects
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Implementation and Evaluation of Network Interface and Message Passing Services for TianHe-1A Supercomputer
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Occupancy Sampling for Terabit CEE Switches
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Express Cube Topologies for on-Chip Interconnects
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Network congestion avoidance through Speculative Reservation
inferred← citeshttps://doi.org/10.1109/hpca.2012.6169048openalex-snapshot
Network within a network approach to create a scalable high-radix router microarchitecture
inferred← citeshttps://doi.org/10.1109/hpca.2013.6522334openalex-snapshot
Breaking the on-chip latency barrier using SMART
inferred← citeshttps://doi.org/10.1109/hpca.2013.6522344openalex-snapshot
Scaling towards kilo-core processors with asymmetric high-radix topologies
inferred← citeshttps://doi.org/10.1109/hpca.2014.6835940openalex-snapshot
MP3: Minimizing performance penalty for power-gating of Clos network-on-chip
inferred← citeshttps://doi.org/10.1109/hpca.2015.7056051openalex-snapshot
Overcoming far-end congestion in large-scale networks
inferred← citeshttps://doi.org/10.1109/hpca.2017.38openalex-snapshot
High-Bandwidth Low-Latency Approximate Interconnection Networks
inferred← citeshttps://doi.org/10.1109/hpca51647.2021.00064openalex-snapshot
BoomGate: Deadlock Avoidance in Non-Minimal Routing for High-Radix Networks
inferred← citeshttps://doi.org/10.1109/hpca56546.2023.10071059openalex-snapshot
VVQ: Virtualizing Virtual Channel for Cost-Efficient Protocol Deadlock Avoidance
inferred← citeshttps://doi.org/10.1109/i-span.2008.16openalex-snapshot
Reliable Opto-Electronic Hybrid Interconnection Network
inferred← citeshttps://doi.org/10.1109/iccad.2008.4681630openalex-snapshot
Advancing supercomputer performance through interconnection topology synthesis
inferred← citeshttps://doi.org/10.1109/icct58878.2023.10347065openalex-snapshot
A Non-Blocking System-Area Network with Multiple Direct Channels
inferred← citeshttps://doi.org/10.1109/icppw.2016.33openalex-snapshot
End-to-End Modeling and Optimization of Power Consumption in HPC Interconnects
inferred← citeshttps://doi.org/10.1109/icppw.2017.33openalex-snapshot
Improving Valiant Routing for Slim Fly Networks
inferred← citeshttps://doi.org/10.1109/igcc.2012.6322279openalex-snapshot
Power efficient photonic networks for many-core architectures
inferred← citeshttps://doi.org/10.1109/ipdps.2017.110openalex-snapshot
FlexVC: Flexible Virtual Channel Management in Low-Diameter Networks
inferred← citeshttps://doi.org/10.1109/ipdps.2017.15openalex-snapshot
A Scalable and Resilient Microarchitecture Based on Multiport Binding for High-Radix Router Design
inferred← citeshttps://doi.org/10.1109/isca.2008.19openalex-snapshot
Technology-Driven, Highly-Scalable Dragonfly Topology
inferred← citeshttps://doi.org/10.1109/isca.2012.6237014openalex-snapshot
A micro-architectural analysis of switched photonic multi-chip interconnects
inferred← citeshttps://doi.org/10.1109/isca.2012.6237016openalex-snapshot
A case for random shortcut topologies for HPC interconnects
inferred← citeshttps://doi.org/10.1109/isca.2018.00065openalex-snapshot
TCEP: Traffic Consolidation for Energy-Proportional High-Radix Networks
inferred← citeshttps://doi.org/10.1109/isca45697.2020.00023openalex-snapshot
Think Fast: A Tensor Streaming Processor (TSP) for Accelerating Deep Learning Workloads
inferred← citeshttps://doi.org/10.1109/isca45697.2020.00085openalex-snapshot
An In-Network Architecture for Accelerating Shared-Memory Multiprocessor Collectives
inferred← citeshttps://doi.org/10.1109/iscc.2012.6249339openalex-snapshot
Honeyguide: A VM migration-aware network topology for saving energy consumption in data center networks
inferred← citeshttps://doi.org/10.1109/ispass.2018.00017openalex-snapshot
SuperSim: Extensible Flit-Level Simulation of Large-Scale Interconnection Networks
inferred← citeshttps://doi.org/10.1109/iwia.2007.8openalex-snapshot
Impact of Predictive Switching in 2-D Torus Networks
inferred← citeshttps://doi.org/10.1109/jetcas.2012.2193936openalex-snapshot
Swizzle-Switch Networks for Many-Core Systems
inferred← citeshttps://doi.org/10.1109/jsac.2014.140109openalex-snapshot
Distributed Adaptive Routing Convergence to Non-Blocking DCN Routing Assignments
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A 0.6 mW/Gb/s, 6.4–7.2 Gb/s Serial Link Receiver Using Local Injection-Locked Ring Oscillators in 90 nm CMOS
inferred← citeshttps://doi.org/10.1109/micro.2014.45openalex-snapshot
Hi-Rise: A High-Radix Switch for 3D Integration with Single-Cycle Arbitration
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Contention-based congestion management in large-scale networks
inferred← citeshttps://doi.org/10.1109/mm.2009.5openalex-snapshot
Cost-Efficient Dragonfly Topology for Large-Scale Systems
inferred← citeshttps://doi.org/10.1109/mm.2011.97openalex-snapshot
Tianhe-1A Interconnect and Message-Passing Services
inferred← citeshttps://doi.org/10.1109/mm.2014.56openalex-snapshot
The Combined Input-Output Queued Crossbar Architecture for High-Radix On-Chip Switches
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A New Family of Hybrid Topologies for Large-Scale Interconnection Networks
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Exploring concentration and channel slicing in on-chip network router
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Memory-centric system interconnect design with Hybrid Memory Cubes
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Cabinet Layout Optimization of Supercomputer Topologies for Shorter Cable Length
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Exploiting Wiring Resources on Interconnection Network: Increasing Path Diversity
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Load Balancing for Data-Parallel Applications on Network-on-Chip Enabled Multi-processor Platform
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Optimal Configuration of High-Radix Combined Switches
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FT-RUFT: A Performance and Fault-Tolerant Efficient Indirect Topology
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The Efficient In-band Management for Interconnect Network in Tianhe-2 System
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Adaptive Routing in High-Radix Clos Network
inferred← citeshttps://doi.org/10.1109/sc.2008.5219754openalex-snapshot
High-radix crossbar switches enabled by Proximity Communication
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Cray Cascade: A scalable HPC system based on a Dragonfly network
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Looking under the hood of the IBM Blue Gene/Q network
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Slim Fly: A Cost Effective Low-Diameter Network Topology
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Exploiting Idle Resources in a High-Radix Switch for Supplemental Storage
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An Efficient Hybrid-Switched Network-on-Chip for Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/tcad.2011.2176730openalex-snapshot
Crossbar NoCs Are Scalable Beyond 100 Nodes
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H OEIN: A Hierarchical Hybrid Optical/Electrical Interconnection Network for Exascale Computing Systems
inferred← citeshttps://doi.org/10.1109/tpds.2015.2430863openalex-snapshot
A Family of Fault-Tolerant Efficient Indirect Topologies
inferred← citeshttps://doi.org/10.1109/tpds.2018.2873337openalex-snapshot
A Cost-Efficient Router Architecture for HPC Inter-Connection Networks: Design and Implementation
inferred← citeshttps://doi.org/10.1109/tvlsi.2011.2148131openalex-snapshot
A Comparative Study of 20-Gb/s NRZ and Duobinary Signaling Using Statistical Analysis
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Reducing Wire and Energy Overheads of the SMART NoC Using a Setup Request Network
inferred← citeshttps://doi.org/10.1134/s0005117910120131openalex-snapshot
An invariant extension method for system area networks of multicore computational systems. An ideal system network
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A new form of an unblockable network
inferred← citeshttps://doi.org/10.1145/1188455.1188552openalex-snapshot
Interconnect routing and scheduling---Adaptive routing in high-radix clos network
inferred← citeshttps://doi.org/10.1145/1394608.1382129openalex-snapshot
Technology-Driven, Highly-Scalable Dragonfly Topology
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Indirect adaptive routing on large scale interconnection networks
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Indirect adaptive routing on large scale interconnection networks
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Low-cost router microarchitecture for on-chip networks
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Energy proportional datacenter networks
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Energy proportional datacenter networks
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The role of optics in future high radix switch design
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The role of optics in future high radix switch design
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Exploiting communication and packaging locality for cost-effective large scale networks
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A micro-architectural analysis of switched photonic multi-chip interconnects
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A case for random shortcut topologies for HPC interconnects
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Distributed adaptive routing for big-data applications running on data center networks
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The power 775 architecture at scale
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Evaluating on-die interconnects for a 4 TB/s router
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Channel reservation protocol for over-subscribed channels and destinations
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Scalable high-radix router microarchitecture using a network switch organization
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A synthetic task model for HPC-grade optical network performance evaluation
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Locality-oblivious cache organization leveraging single-cycle multi-hop NoCs
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Locality-oblivious cache organization leveraging single-cycle multi-hop NoCs
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Locality-oblivious cache organization leveraging single-cycle multi-hop NoCs
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Security Vulnerability in Processor-Interconnect Router Design
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A Universal Approach to Data Center Network Design
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Network endpoint congestion control for fine-grained communication
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Electro-Photonic NoC Designs for Kilocore Systems
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Interconnection Networks in Petascale Computer Systems
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Bandwidth steering in HPC using silicon nanophotonics
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A software-defined tensor streaming multiprocessor for large-scale machine learning
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Optimizing All-to-All Collective Communication with Fault Tolerance on Torus Networks
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Design of Interposer Interconnection Network Based on High-Radix Interposer Routers
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Topological Reserves of Flattened Networks
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On-Chip Dynamic Resource Management
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Optical network technologies for HPC: computer-architects point of view
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Modular router architecture for high-performance interconnection networks
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Main Problem Directions in the Field of Domestic Element Base of Supercomputers
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High Performance Datacenter Networks: Architectures, Algorithms, and Opportunities
inferred← citeshttps://doi.org/10.2200/s00772ed1v01y201704cac040openalex-snapshot
On-Chip Networks, Second Edition
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Multichannel non-blocking system area network with direct channels
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Multichannel non-blocking system area network with direct channels
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Performance Analysis of Overcoming Far-end Congestion in Large-Scale Networks
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High-radix crossbar switches enabled by proximity communication
inferred← citeshttps://doi.org/10.5555/1509456.1509579openalex-snapshot
Advancing supercomputer performance through interconnection topology synthesis
inferred← citeshttps://doi.org/10.5555/2388996.2389136openalex-snapshot
Cray cascade: a scalable HPC system based on a Dragonfly network
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Design of energy-efficient vector units for in-order cores
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