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Hi-Rise: A High-Radix Switch for 3D Integration with Single-Cycle Arbitration

https://doi.org/10.1109/micro.2014.45
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/26.780463openalex-snapshot
Achieving 100% throughput in an input-queued switch
inferredcites →https://doi.org/10.1109/90.769767openalex-snapshot
The iSLIP scheduling algorithm for input-queued switches
inferredcites →https://doi.org/10.1109/glocom.1999.829968openalex-snapshot
A fast arbitration scheme for terabit packet switches
inferredcites →https://doi.org/10.1109/hpca.2009.4798234openalex-snapshot
A low-radix and low-diameter 3D interconnection network design
inferredcites →https://doi.org/10.1109/hpca.2013.6522344openalex-snapshot
Scaling towards kilo-core processors with asymmetric high-radix topologies
inferredcites →https://doi.org/10.1109/icc.2003.1203927openalex-snapshot
A two-dimensional scalable crossbar matrix switch architecture
inferredcites →https://doi.org/10.1109/infcom.2000.832228openalex-snapshot
FIRM: a class of distributed scheduling algorithms for high-speed ATM switches with multiple input queues
inferredcites →https://doi.org/10.1109/isca.2005.35openalex-snapshot
Microarchitecture of a High-Radix Router
inferredcites →https://doi.org/10.1109/isca.2006.40openalex-snapshot
The BlackWidow High-Radix Clos Network
inferredcites →https://doi.org/10.1109/isca.2008.19openalex-snapshot
Technology-Driven, Highly-Scalable Dragonfly Topology
inferredcites →https://doi.org/10.1109/isscc.2010.5434077openalex-snapshot
A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS
inferredcites →https://doi.org/10.1109/isscc.2012.6176970openalex-snapshot
Centip3De: A 3930DMIPS/W configurable near-threshold 3D stacked system with 64 ARM Cortex-M3 cores
inferredcites →https://doi.org/10.1109/isscc.2012.6177098openalex-snapshot
A 4.5Tb/s 3.4Tb/s/W 64×64 switch fabric with self-updating least-recently-granted priority and quality-of-service arbitration in 45nm CMOS
inferredcites →https://doi.org/10.1109/isvlsi.2009.53openalex-snapshot
High Performance Non-blocking Switch Design in 3D Die-Stacking Technology
inferredcites →https://doi.org/10.1109/jetcas.2012.2193936openalex-snapshot
Swizzle-Switch Networks for Many-Core Systems
inferredcites →https://doi.org/10.1109/micro.2004.28openalex-snapshot
Pinpointing Representative Portions of Large Intel® Itanium® Programs with Dynamic Instrumentation
inferredcites →https://doi.org/10.1109/micro.2007.15openalex-snapshot
Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures
inferredcites →https://doi.org/10.1109/micro.2007.29openalex-snapshot
Flattened Butterfly Topology for On-Chip Networks
inferredcites →https://doi.org/10.1109/micro.2010.18openalex-snapshot
Probabilistic Distance-Based Arbitration: Providing Equality of Service for Many-Core CMPs
inferredcites →https://doi.org/10.1109/mm.2007.4378780openalex-snapshot
On-Chip Interconnection Architecture of the Tile Processor
inferredcites →https://doi.org/10.1145/1080695.1070005openalex-snapshot
Microarchitecture of a High-Radix Router
inferredcites →https://doi.org/10.1145/1150019.1136488openalex-snapshot
The BlackWidow High-Radix Clos Network
inferredcites →https://doi.org/10.1145/1150019.1136497openalex-snapshot
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
inferredcites →https://doi.org/10.1145/1186736.1186737openalex-snapshot
SPEC CPU2006 benchmark descriptions
inferredcites →https://doi.org/10.1145/1250662.1250679openalex-snapshot
Flattened butterfly
inferredcites →https://doi.org/10.1145/1250662.1250680openalex-snapshot
A novel dimensionally-decomposed router for on-chip communication in 3D architectures
inferredcites →https://doi.org/10.1145/1278480.1278667openalex-snapshot
Thousand core chips
inferredcites →https://doi.org/10.1145/1362622.1362630openalex-snapshot
Age-based packet arbitration in large-radix k -ary n -cubes
inferredcites →https://doi.org/10.1145/1394608.1382129openalex-snapshot
Technology-Driven, Highly-Scalable Dragonfly Topology
inferredcites →https://doi.org/10.1145/1394608.1382143openalex-snapshot
MIRA
inferredcites →https://doi.org/10.1145/161541.161736openalex-snapshot
High-speed switch scheduling for local-area networks
inferredcites →https://doi.org/10.1145/1669112.1669150openalex-snapshot
Application-aware prioritization mechanisms for on-chip networks
inferredcites →https://doi.org/10.1145/2228360.2228432openalex-snapshot
High radix self-arbitrating switch fabric with multiple arbitration schemes and quality of service

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-319-49583-5_12openalex-snapshot
Graphein: A Novel Optical High-Radix Switch Architecture for 3D Integration
inferred← citeshttps://doi.org/10.1007/978-981-10-3159-5_17openalex-snapshot
A High-Radix Switch Architecture Based on Silicon Photonic and 3D Integration
inferred← citeshttps://doi.org/10.1016/bs.adcom.2018.03.009openalex-snapshot
Topology Specialization for Networks-on-Chip in the Dark Silicon Era
inferred← citeshttps://doi.org/10.1016/j.neucom.2017.12.073openalex-snapshot
A scalable smart router architecture with intelligent adaptive routing and fault-tolerant management
inferred← citeshttps://doi.org/10.1109/ipdps47924.2020.00013openalex-snapshot
Accelerated Reply Injection for Removing NoC Bottleneck in GPGPUs
inferred← citeshttps://doi.org/10.1109/lca.2015.2448532openalex-snapshot
Dynamic Resource Sharing for High-Performance 3-D Networks-on-Chip
inferred← citeshttps://doi.org/10.1109/tc.2021.3076431openalex-snapshot
Hybrid Memory Buffer Microarchitecture for High-Radix Routers
inferred← citeshttps://doi.org/10.1145/2818950.2818951openalex-snapshot
Interconnect-Memory Challenges for Multi-chip, Silicon Interposer Systems
inferred← citeshttps://doi.org/10.1145/2925426.2926275openalex-snapshot
Galaxyfly
inferred← citeshttps://doi.org/10.1145/3079856.3080251openalex-snapshot
There and Back Again
inferred← citeshttps://doi.org/10.1145/3140659.3080251openalex-snapshot
There and Back Again
inferred← citeshttps://doi.org/10.1145/3410463.3414627openalex-snapshot
Transmuter
inferred← citeshttps://doi.org/10.3850/9783981537079_0513openalex-snapshot
Fault-Tolerant 3-D Network-on-Chip Design using Dynamic Link Sharing
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