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Enabling high-speed turbo-decoding through concurrent interleaving

https://doi.org/10.1109/iscas.2002.1009986
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Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/icc.1993.397441openalex-snapshot
Near Shannon limit error-correcting coding and decoding: Turbo-codes. 1
inferredcites →https://doi.org/10.1109/sips.2000.886725openalex-snapshot
A high-speed MAP architecture with optimized memory size and power consumption

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.5281/zenodo.40373openalex-extracted
Efficient Parallel Memory Organization For Turbo Decoders
inferred← citeshttps://doi.org/10.1007/978-1-4614-8310-6_3openalex-snapshot
Turbo Decoder with Parallel Processing
inferred← citeshttps://doi.org/10.1007/978-3-540-39762-5_44openalex-snapshot
Architecture-Driven Voltage Scaling for High-Throughput Turbo-Decoders
inferred← citeshttps://doi.org/10.1023/b:vlsi.0000047272.75049.0eopenalex-snapshot
A Scalable System Architecture for High-Throughput Turbo-Decoders
inferred← citeshttps://doi.org/10.1109/asap.2011.6043259openalex-snapshot
High-throughput Contention-Free concurrent interleaver architecture for multi-standard turbo decoder
inferred← citeshttps://doi.org/10.1109/dsd.2004.1333294openalex-snapshot
Scalable and area efficient concurrent interleaver for high throughput turbo-decoders
inferred← citeshttps://doi.org/10.1109/icassp.2003.1202441openalex-snapshot
Concurrent interleaving architectures for high-throughput channel coding
inferred← citeshttps://doi.org/10.1109/icassp.2003.1202445openalex-snapshot
Efficient interleaver memory architectures for serial turbo decoding
inferred← citeshttps://doi.org/10.1109/icassp.2013.6638157openalex-snapshot
On-chip implementation of memory mapping algorithm to support flexible decoder architecture
inferred← citeshttps://doi.org/10.1109/icassp.2014.6854561openalex-snapshot
Embedding polynomial time memory mapping and routing algorithms on-chip to design configurable decoder architectures
inferred← citeshttps://doi.org/10.1109/icecs.2002.1046443openalex-snapshot
Optimized concurrent interleaving architecture for high-throughput turbo-decoding
inferred← citeshttps://doi.org/10.1109/iscas.2005.1464950openalex-snapshot
Network-on-Chip-Centric Approach to Interleaving in High Throughput Channel Decoders
inferred← citeshttps://doi.org/10.1109/iscas.2007.378627openalex-snapshot
Evaluation of High Throughput Turbo-Decoder Architectures
inferred← citeshttps://doi.org/10.1109/isocc.2012.6407111openalex-snapshot
A 516Mb/s 0.2nJ/bit/iter variable-block-size turbo decoder for 3GPP LTE-A system
inferred← citeshttps://doi.org/10.1109/jproc.2007.895202openalex-snapshot
Iterative Decoding of Concatenated Convolutional Codes: Implementation Issues
inferred← citeshttps://doi.org/10.1109/jssc.2009.2038428openalex-snapshot
Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture
inferred← citeshttps://doi.org/10.1109/milcom.2006.301998openalex-snapshot
Support MUOS All IP Services with the FEC Enhancement
inferred← citeshttps://doi.org/10.1109/milcom.2006.302027openalex-snapshot
A Gigabit/Second Turbo Decoder on Field Programmable Gate Array: Supporting Tsat Channel Coding Requirement
inferred← citeshttps://doi.org/10.1109/pimrc.2003.1259097openalex-snapshot
Parallel memory access in turbo decoders
inferred← citeshttps://doi.org/10.1109/sips.2002.1049701openalex-snapshot
A scalable system architecture for high-throughput turbo-decoders
inferred← citeshttps://doi.org/10.1109/tcsi.2010.2046257openalex-snapshot
Turbo NOC: A Framework for the Design of Network-on-Chip-Based Turbo Decoder Architectures
inferred← citeshttps://doi.org/10.1109/tcsi.2014.2309810openalex-snapshot
Parallel Interleaver Design for a High throughput HSPA+/LTE Multi-Standard Turbo Decoder
inferred← citeshttps://doi.org/10.1109/tcsii.2008.919510openalex-snapshot
A Flexible UMTS-WiMax Turbo Decoder Architecture
inferred← citeshttps://doi.org/10.1109/tit.2004.833353openalex-snapshot
Mapping Interleaving Laws to Parallel Turbo and LDPC Decoder Architectures
inferred← citeshttps://doi.org/10.1109/tsp.2013.2264057openalex-snapshot
A First Step Toward On-Chip Memory Mapping for Parallel Turbo and LDPC Decoders: A Polynomial Time Mapping Algorithm
inferred← citeshttps://doi.org/10.1155/2008/319095openalex-snapshot
A Programmable Max‐Log‐MAP Turbo Decoder Implementation
inferred← citeshttps://doi.org/10.1155/2010/513104openalex-snapshot
A Programmable, Scalable-Throughput Interleaver
inferred← citeshttps://doi.org/10.35429/jsta.2019.15.5.29.41openalex-snapshot
Técnicas para la implementación de turbo decodificadores con baja latencia
inferred← citeshttps://doi.org/10.3850/9783981537079_0196openalex-snapshot
A Dynamically Reconfigurable ECC Decoder Architecture
inferred← citeshttps://doi.org/10.5194/ars-2-181-2004openalex-snapshot
Application driven evaluation of network on chip architectures forcation parallel signal processing
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