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Network-on-Chip-Centric Approach to Interleaving in High Throughput Channel Decoders
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1023/b:vlsi.0000047272.75049.0eopenalex-snapshot
A Scalable System Architecture for High-Throughput Turbo-Decoders
inferredcites →https://doi.org/10.1049/el:20020148openalex-snapshot
Parallel turbo coding interleavers: avoiding collisions in accesses to storage elements
inferredcites →https://doi.org/10.1049/el:20020916openalex-snapshot
Design of dividable interleaver for parallel decoding in turbo codes
inferredcites →https://doi.org/10.1109/aspdac.2004.1337619openalex-snapshot
Design methodology for IRA codes
inferredcites →https://doi.org/10.1109/dsd.2004.1333294openalex-snapshot
Scalable and area efficient concurrent interleaver for high throughput turbo-decoders
inferredcites →https://doi.org/10.1109/glocom.2001.965980openalex-snapshot
Optimizing iterative decoding of low-density parity check codes on programmable pipelined parallel architectures
inferredcites →https://doi.org/10.1109/icassp.2003.1202441openalex-snapshot
Concurrent interleaving architectures for high-throughput channel coding
inferredcites →https://doi.org/10.1109/icecs.2002.1046443openalex-snapshot
Optimized concurrent interleaving architecture for high-throughput turbo-decoding
inferredcites →https://doi.org/10.1109/isca.1992.753324openalex-snapshot
The Turn Model for Adaptive Routing
inferredcites →https://doi.org/10.1109/iscas.2002.1009986openalex-snapshot
Enabling high-speed turbo-decoding through concurrent interleaving
inferredcites →https://doi.org/10.1109/lcomm.2004.823364openalex-snapshot
Mapping Interleaving Laws to Parallel Turbo Decoder Architectures
inferredcites →https://doi.org/10.1109/sips.2002.1049697openalex-snapshot
A 54 Mbps (3,6)-regular FPGA LDPC decoder
inferredcites →https://doi.org/10.1109/sips.2002.1049708openalex-snapshot
Parallel interleaving on parallel DSP architectures
inferredcites →https://doi.org/10.1109/tc.1987.1676939openalex-snapshot
Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
inferredcites →https://doi.org/10.1109/vtc.2001.957178openalex-snapshot
High-performance low-memory interleaver banks for turbo-codes
inferredcites →https://doi.org/10.1145/139669.140384openalex-snapshot
The turn model for adaptive routing
inferredcites →https://doi.org/10.5555/1015090.1015205openalex-snapshot
Design methodology for IRA codes
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.5281/zenodo.40373openalex-extracted
Efficient Parallel Memory Organization For Turbo Decoders
inferred← citeshttps://doi.org/10.1007/978-1-4614-8030-3_7openalex-snapshot
Low-Density Parity-Check Codes
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MP-SoC/NoC Architectures for Error Correction
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Fat Tree NoC Design and Synthesis
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Reducing the Dissipated Energy in Multi-standard Turbo and LDPC Decoders
inferred← citeshttps://doi.org/10.1007/s11265-013-0733-7openalex-snapshot
Improving Network-on-Chip-based Turbo Decoder Architectures
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Five Stage Telecommunication Switching Design and Synthesis
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Machine Learning Based Resource Utilization and Pre-estimation for Network on Chip (NoC) Communication
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Hardware Design and Realization for Iteratively Decodable Codes
inferred← citeshttps://doi.org/10.1016/j.micpro.2010.08.004openalex-snapshot
On chip interconnects for multiprocessor turbo decoding architectures
inferred← citeshttps://doi.org/10.1016/j.procs.2015.04.119openalex-snapshot
Design and FPGA Synthesis of Three Stage Telecommunication Switching in HDL Environment
inferred← citeshttps://doi.org/10.1016/j.vlsi.2014.11.003openalex-snapshot
Exploiting generalized de-Bruijn/Kautz topologies for flexible iterative channel code decoder architectures
inferred← citeshttps://doi.org/10.1049/el:20062209openalex-snapshot
Bandwidth reduction of extrinsic information exchange in turbo decoding
inferred← citeshttps://doi.org/10.1049/iet-cdt.2010.0177openalex-snapshot
Parallel low-density parity check decoding on a network-on-chip-based multiprocessor platform
inferred← citeshttps://doi.org/10.1109/asap.2011.6043259openalex-snapshot
High-throughput Contention-Free concurrent interleaver architecture for multi-standard turbo decoder
inferred← citeshttps://doi.org/10.1109/ccca.2011.6031404openalex-snapshot
Network interface sharing for SoCs based NoC
inferred← citeshttps://doi.org/10.1109/date.2007.364668openalex-snapshot
Butterfly and Benes-Based on-Chip Communication Networks for Multiprocessor Turbo Decoding
inferred← citeshttps://doi.org/10.1109/date.2010.5457035openalex-snapshot
A 150Mbit/s 3GPP LTE Turbo code decoder
inferred← citeshttps://doi.org/10.1109/date.2012.6176715openalex-snapshot
A Network-on-Chip-based turbo/LDPC decoder architecture
inferred← citeshttps://doi.org/10.1109/iccs.2010.5686499openalex-snapshot
A multi-mode 3GPP-LTE/HSDPA turbo decoder
inferred← citeshttps://doi.org/10.1109/icsamos.2009.5289227openalex-snapshot
High-throughput flexible constraint length Viterbi decoders on de Bruijn, shuffle-exchange and butterfly connected architectures
inferred← citeshttps://doi.org/10.1109/innovations.2013.6544409openalex-snapshot
PNOC: Implementation on Verilog for FPGA
inferred← citeshttps://doi.org/10.1109/iscas.2007.378627openalex-snapshot
Evaluation of High Throughput Turbo-Decoder Architectures
inferred← citeshttps://doi.org/10.1109/iscas.2013.6572102openalex-snapshot
Parallel interleaver architecture with new scheduling scheme for high throughput configurable turbo decoder
inferred← citeshttps://doi.org/10.1109/jsyst.2011.2173614openalex-snapshot
A System-Level Modeling Methodology for Performance-Driven Component Selection in Multicore Architectures
inferred← citeshttps://doi.org/10.1109/lpt.2007.903636openalex-snapshot
Error-Resilient Performance of Dirac Video Codec Over Packet-Erasure Channel
inferred← citeshttps://doi.org/10.1109/norchp.2005.1596994openalex-snapshot
Requirements for network-on-chip benchmarking
inferred← citeshttps://doi.org/10.1109/pdp.2014.85openalex-snapshot
Rediscovering Logarithmic Diameter Topologies for Low Latency Network-on-Chip-Based Applications
inferred← citeshttps://doi.org/10.1109/sbac-pad.2009.9openalex-snapshot
Parallel LDPC Decoding on a Network-on-Chip Based Multiprocessor Platform
inferred← citeshttps://doi.org/10.1109/tcsi.2010.2046257openalex-snapshot
Turbo NOC: A Framework for the Design of Network-on-Chip-Based Turbo Decoder Architectures
inferred← citeshttps://doi.org/10.1109/tcsi.2012.2221216openalex-snapshot
VLSI Implementation of a Multi-Mode Turbo/LDPC Decoder Architecture
inferred← citeshttps://doi.org/10.1109/tcsi.2014.2309810openalex-snapshot
Parallel Interleaver Design for a High throughput HSPA+/LTE Multi-Standard Turbo Decoder
inferred← citeshttps://doi.org/10.1109/turbocoding.2008.4658686openalex-snapshot
Bit-width optimization of extrinsic information in turbo decoder
inferred← citeshttps://doi.org/10.1109/tvlsi.2011.2181545openalex-snapshot
Design and Implementation of an On-Chip Permutation Network for Multiprocessor System-On-Chip
inferred← citeshttps://doi.org/10.1145/1132952.1132953openalex-snapshot
A survey of research and practices of Network-on-chip
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A Programmable Max‐Log‐MAP Turbo Decoder Implementation
inferred← citeshttps://doi.org/10.1155/2010/513104openalex-snapshot
A Programmable, Scalable-Throughput Interleaver
inferred← citeshttps://doi.org/10.1587/elex.7.861openalex-snapshot
ProMINoC: An efficient Network-on-Chip design for flexible data permutation
inferred← citeshttps://doi.org/10.35429/jsta.2019.15.5.29.41openalex-snapshot
Técnicas para la implementación de turbo decodificadores con baja latencia
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Design And Enactment Of Dynamically Reconfigurable Bus Enhanced Noc Architecture For Emerging Digital System
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A Reconfigurable Outer Modem Platform for Future Communications Systems
inferred← citeshttps://doi.org/10.48550/arxiv.1105.1014openalex-snapshot
Improving Network-on-Chip-based turbo decoder architectures
inferred← citeshttps://doi.org/10.5120/13778-1649openalex-snapshot
Design and Simulation of Output Queuing with the Middle stage Buffered (OQMB) Close Packet Switching Network
inferred← citeshttps://doi.org/10.5555/1870926.1871268openalex-snapshot
A 150Mbit/s 3GPP LTE turbo code decoder
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Contribution to the architecture and implementation of Bi-NoC routers for multi-synchronous GALS systems
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