On the public citation graph
High Speed Generic Network Interface for Network on Chip Using Ping Pong Buffers
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/11802839_37openalex-snapshot
Generic Network Interfaces for Plug and Play NoC Based Architecture
inferredcites →https://doi.org/10.1007/978-3-540-78153-0_19openalex-snapshot
A Generic Network Interface Architecture for a Networked Processor Array (NePA)
inferredcites →https://doi.org/10.1016/j.vlsi.2007.12.002openalex-snapshot
Network-on-Chip design and synthesis outlook
inferredcites →https://doi.org/10.1109/2.976921openalex-snapshot
Networks on chips: a new SoC paradigm
inferredcites →https://doi.org/10.1109/async.2006.16openalex-snapshot
Design of On-chip and Off-chip Interfaces for a GALS NoC Architecture
inferredcites →https://doi.org/10.1109/async.2009.13openalex-snapshot
Design and Implementation of a GALS Adapter for ANoC Based Architectures
inferredcites →https://doi.org/10.1109/dtis.2010.5487541openalex-snapshot
Design and implementation of network interface compatible OCP For packet based NOC
inferredcites →https://doi.org/10.1109/infcom.1998.665104openalex-snapshot
Doubling memory bandwidth for network buffers
inferredcites →https://doi.org/10.1109/isicir.2007.4441820openalex-snapshot
Interfacing Cores and Routers in Network-on-Chip Using GALS
inferredcites →https://doi.org/10.1109/isqed.2001.915211openalex-snapshot
Scripting for EDA tools: a case study
inferredcites →https://doi.org/10.1109/isvlsi.2010.44openalex-snapshot
A High Throughput Low Power FIFO Used for GALS NoC Buffers
inferredcites →https://doi.org/10.1109/norchp.2009.5397837openalex-snapshot
Efficient network interface architecture for network-on-chips
inferredcites →https://doi.org/10.1109/ssd.2011.5767464openalex-snapshot
A low power network interface for network on chip
inferredcites →https://doi.org/10.1109/vlsisoc.2010.5642627openalex-snapshot
Network interface to synchronize multiple packets on NoC-based Systems-on-Chip
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-319-90023-0_12openalex-snapshot
Taming the Memory Demand Complexity of Adaptive Vision Algorithms
inferred← citeshttps://doi.org/10.1016/j.jfranklin.2017.07.037openalex-snapshot
System-on-a-chip (SoC)-based hardware acceleration for foreground and background identification
inferred← citeshttps://doi.org/10.1049/iet-cdt.2014.0075openalex-snapshot
Power‐efficient real‐time solution for adaptive vision algorithms
inferred← citeshttps://doi.org/10.1109/apccas55924.2022.10090323openalex-snapshot
A Dynamic JPEG CODEC with Adaptive Quantization Table for Frame Storage Compression
inferred← citeshttps://doi.org/10.1109/ccdc52312.2021.9601458openalex-snapshot
Design of verification platform for FPGA shape selection algorithm and its application in grain classification
inferred← citeshttps://doi.org/10.1109/ccece.2013.6567787openalex-snapshot
Design of a low power network interface for Network on chip
inferred← citeshttps://doi.org/10.1109/ciycee67631.2025.11308863openalex-snapshot
Development of an ion current readout system for high-resolution mass spectrometer based on ZYNQ
inferred← citeshttps://doi.org/10.1109/eleco.2015.7394449openalex-snapshot
Design and physical implementation of a data transfer interface used in network on chip
inferred← citeshttps://doi.org/10.1109/icccas65806.2025.11102327openalex-snapshot
Enhancing Convolutional Neural Networks With Depth-Aware Architectures: a Systolic Array Approach for Efficient Hardware Implementation
inferred← citeshttps://doi.org/10.1109/iccvit63928.2024.10872500openalex-snapshot
FPGA-based Moving Object Detection Leveraging Frame Difference and Morphological Filtering
inferred← citeshttps://doi.org/10.1109/ictai56018.2022.00095openalex-snapshot
Evaluating a New Attention Framework Based on Matrix Blocking for Attention Models on FPGAs
inferred← citeshttps://doi.org/10.1109/iscas.2016.7527462openalex-snapshot
DMNI: A specialized network interface for NoC-based MPSoCs
inferred← citeshttps://doi.org/10.1109/nelex69209.2026.11590593openalex-snapshot
High-Level Synthesis Based DDR4 Memory Controller with Refresh-Aware Optimization for FPGA Systems
inferred← citeshttps://doi.org/10.1109/tcsi.2023.3311486openalex-snapshot
A Spatio-Temporal Video Denoising Co-Processor With Adaptive Codec
inferred← citeshttps://doi.org/10.1145/3649827openalex-snapshot
PROMPT: A Fast and Extensible Memory Profiling Framework
inferred← citeshttps://doi.org/10.17760/d20018704openalex-snapshot
High-performance power-efficient solutions for embedded vision computing
inferred← citeshttps://doi.org/10.20868/upm.thesis.66238openalex-snapshot
FPGA-based acceleration of tracking algorithm to improve Parkinson's patients quality of life
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