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Design of On-chip and Off-chip Interfaces for a GALS NoC Architecture
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-3-540-39762-5_20openalex-snapshot
Static Implementation of QDI Asynchronous Primitives
inferredcites →https://doi.org/10.1049/ip-cdt:20030830openalex-snapshot
Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip
inferredcites →https://doi.org/10.1109/async.1998.666491openalex-snapshot
ASPRO-216: a standard-cell Q.D.I. 16-bit RISC asynchronous microprocessor
inferredcites →https://doi.org/10.1109/async.2000.836786openalex-snapshot
An on-chip dynamically recalibrated delay line for embedded self-timed systems
inferredcites →https://doi.org/10.1109/async.2000.836791openalex-snapshot
Practical design of globally-asynchronous locally-synchronous systems
inferredcites →https://doi.org/10.1109/async.2001.914075openalex-snapshot
Delay insensitive system-on-chip interconnect using 1-of-4 data encoding
inferredcites →https://doi.org/10.1109/async.2002.1000297openalex-snapshot
Point to point GALS interconnect
inferredcites →https://doi.org/10.1109/async.2004.1299298openalex-snapshot
Data synchronization issues in GALS SoCs
inferredcites →https://doi.org/10.1109/async.2005.10openalex-snapshot
An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework
inferredcites →https://doi.org/10.1109/async.2005.11openalex-snapshot
An Asynchronous Router for Multiple Service Levels Networks on Chip
inferredcites →https://doi.org/10.1109/async.2005.7openalex-snapshot
A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip
inferredcites →https://doi.org/10.1109/conect.2003.1231470openalex-snapshot
Nexus: an asynchronous crossbar interconnect for synchronous system-on-chip designs
inferredcites →https://doi.org/10.1109/mm.2002.1044296openalex-snapshot
Chain: a delay-insensitive chip area interconnect
inferredcites →https://doi.org/10.1109/tvlsi.2004.831476openalex-snapshot
Robust interfaces for mixed-timing systems
inferredcites →https://doi.org/10.13140/rg.2.1.4128.7843openalex-snapshot
Globally-Asynchronous Locally-Synchronous Systems
inferredcites →https://doi.org/10.5555/789083.1022751openalex-snapshot
Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip
inferredcites →https://doi.org/10.7907/zmy86-a1w29openalex-snapshot
Programming in VLSI: From Communicating Processes to Delay-Insensitive Circuits
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Power Modeling of a NoC Based Design for High Speed Telecommunication Systems
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Automatic adjustment of a medical imaging data acquisition system to unknown delays in the input communication channels
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Design and Verification of an Asynchronous NoC Router Architecture for GALS Systems
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Quasi delay-insensitive high speed two-phase protocol asynchronous wrapper for network on chips
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Quasi Delay-Insensitive High Speed Two-Phase Protocol Asynchronous Wrapper for Network on Chips
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A Multi-Synchronous Bi-Directional NoC (MBiNoC) architecture with dynamic self-reconfigurable channel for the GALS infrastructure
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Design and verification of an efficient WISHBONE-based network interface for network on chip
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Modified bundled-data as a new protocol for NoC asynchronous links
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A high performance dual clock elastic FIFO network interface for GALS NoC
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A hardware/software platform for QoS bridging over multi-chip NoC-based systems
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On the semantics of communicating hardware processes and their translation into LOTOS for the verification of asynchronous circuits with CADP
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Test methods for crosstalk-induced delay and glitch faults in network-on-chip interconnects implementing asynchronous communication protocols
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A 3 Gb/s multichannel transceiver in 65 nm CMOS technology
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A Design Support Tool Set for Interface Circuits Between Synchronous and Asynchronous Modules
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Robust solution for synchronous communication among multi clock domains
inferred← citeshttps://doi.org/10.1109/apccas.2014.7032705openalex-snapshot
Low delay-variation sub-/near-threshold asynchronous-to-synchronous interface controller for GALS Network-on-Chips
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Efficient Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication
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Formal Verification of CHP Specifications with CADP Illustration on an Asynchronous Network-on-Chip
inferred← citeshttps://doi.org/10.1109/async.2009.13openalex-snapshot
Design and Implementation of a GALS Adapter for ANoC Based Architectures
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An SET Tolerant Tree Arbiter Cell
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Classifying Virtual Channel Access Control Schemes for Asynchronous NoCs
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Timing Domain Crossing using Muller Pipelines
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Design of a low power network interface for Network on chip
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Comparison of dual rail and an enhanced bundled data asynchronous protocols noise robustness in the GALS NoC link application
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Design of a GALS Wrapper for Network on Chip
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Energy-efficient techniques for circuit design in network-on-chip platforms
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Automatic Configuration of a Medical Imaging System to Unknown Delays in Synchronous Input Data Channels
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Associating packets of heterogeneous cores using a synchronizer wrapper for NoCs
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Floorplan-aware hierarchical NoC topology with GALS interfaces
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High Speed Generic Network Interface for Network on Chip Using Ping Pong Buffers
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On restoring data coherence in a GALS system for medical imaging
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Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook
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Multisynchronous and Fully Asynchronous NoCs for GALS Architectures
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ASC, a SystemC Extension for Modeling Asynchronous Systems, and Its Application to an Asynchronous NoC
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Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS Architectures
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QNoC Asynchronous Router with Dynamic Virtual Channel Allocation
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Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC
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Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture
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Reducing NoC Energy Consumption Exploring Asynchronous End-to-end GALS Communication
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Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication
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