On the public citation graph
Effects of MSHR and Prefetch Mechanisms on an On-Chip Cache of the Vector Architecture
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/11403937_5openalex-snapshot
A Performance Evaluation of the Cray X1 for Scientific Applications
inferredcites →https://doi.org/10.1007/11946441_76openalex-snapshot
Implications of Memory Performance for Highly Efficient Supercomputing of Scientific Applications
inferredcites →https://doi.org/10.1007/978-3-540-68743-6_2openalex-snapshot
Implication of Memory Performance in Vector-Parallel and Scalar-Parallel HEC Systems
inferredcites →https://doi.org/10.1007/978-3-540-74384-2_18openalex-snapshot
The Potential of On-Chip Memory Systems for Future Vector Architectures
inferredcites →https://doi.org/10.1109/2.596622openalex-snapshot
When caches aren't enough: data prefetching techniques
inferredcites →https://doi.org/10.1109/conect.2004.1375194openalex-snapshot
Performance evaluation of the Cray X1 distributed shared memory architecture
inferredcites →https://doi.org/10.1109/ipdps.2003.1213087openalex-snapshot
So many states, so little time: verifying memory coherence in the Cray X1
inferredcites →https://doi.org/10.1109/micro.2004.9openalex-snapshot
Cache Refill/Access Decoupling for Vector Machines
inferredcites →https://doi.org/10.1109/mm.2005.20openalex-snapshot
Performance Evaluation of the Cray X1 Distributed Shared-Memory Architecture
inferredcites →https://doi.org/10.1145/115952.115959openalex-snapshot
Data prefetching in multiprocessor vector cache memories
inferredcites →https://doi.org/10.1145/115953.115959openalex-snapshot
Data prefetching in multiprocessor vector cache memories
inferredcites →https://doi.org/10.1145/1188455.1188677openalex-snapshot
S12---The HPC Challenge (HPCC) benchmark suite
inferredcites →https://doi.org/10.1145/1327171.1327173openalex-snapshot
An on-chip cache design for vector processors
inferredcites →https://doi.org/10.1145/181181.181549openalex-snapshot
The effectiveness of caches for vector processors
inferredcites →https://doi.org/10.1145/285930.285979openalex-snapshot
Lockup-free instruction fetch/prefetch cache organization
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-319-07518-1_13openalex-snapshot
The Brand-New Vector Supercomputer, SX-ACE
inferred← citeshttps://doi.org/10.1007/978-3-319-10626-7_5openalex-snapshot
SX-ACE, Brand-New Vector Supercomputer for Higher Sustained Performance I
inferred← citeshttps://doi.org/10.1007/s11227-017-1993-yopenalex-snapshot
Potential of a modern vector supercomputer for practical applications: performance evaluation of SX-ACE
inferred← citeshttps://doi.org/10.1007/s11227-018-2363-0openalex-snapshot
Real-time tsunami inundation forecast system for tsunami disaster prevention and mitigation
inferred← citeshttps://doi.org/10.1109/asicon.2011.6157154openalex-snapshot
A novel hardware prefetching scheme exploiting 2-D spatial locality in multimedia applications
inferred← citeshttps://doi.org/10.1109/cluster.2017.57openalex-snapshot
Performance Evaluation of Quantum ESPRESSO on NEC SX-ACE
inferred← citeshttps://doi.org/10.1109/cluster.2017.65openalex-snapshot
Performance and Power Analysis of SX-ACE Using HP-X Benchmark Programs
inferred← citeshttps://doi.org/10.1109/estimedia.2013.6704506openalex-snapshot
Design and evaluation of a media-oriented vector processor with a multi-banked cache memory
inferred← citeshttps://doi.org/10.1109/tvlsi.2026.3658749openalex-snapshot
PipeCHX: A High-Bandwidth-Low-Latency Hybrid CXL Memory Controller
inferred← citeshttps://doi.org/10.1145/1621960.1621962openalex-snapshot
Performance tuning and analysis of future vector processors based on the roofline model
inferred← citeshttps://doi.org/10.1145/1654059.1654088openalex-snapshot
Performance evaluation of NEC SX-9 using real science and engineering applications
inferred← citeshttps://doi.org/10.14529/jsfi200401openalex-snapshot
Effects of Using a Memory Stalled Core for Handling MPI Communication Overlapping in the SOR Solver on SX-ACE and SX-Aurora TSUBASA
inferred← citeshttps://doi.org/10.1587/transinf.2014edp7227openalex-snapshot
MVP-Cache: A Multi-Banked Cache Memory for Energy-Efficient Vector Processing of Multimedia Applications
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