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Cache Refill/Access Decoupling for Vector Machines
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1016/0167-8191(87)90021-4openalex-snapshot
Architecture and performance of NEC supercomputer SX system
inferredcites →https://doi.org/10.1109/2.30730openalex-snapshot
Dynamic instruction scheduling and the Astronautics ZS-1
inferredcites →https://doi.org/10.1109/2.596622openalex-snapshot
When caches aren't enough: data prefetching techniques
inferredcites →https://doi.org/10.1109/40.918001openalex-snapshot
Imagine: media processing with streams
inferredcites →https://doi.org/10.1109/hpca.1996.501193openalex-snapshot
Decoupled vector architectures
inferredcites →https://doi.org/10.1109/hpca.2004.10007openalex-snapshot
Stream Register Files with Indexed Access
inferredcites →https://doi.org/10.1109/ipdps.2003.1213087openalex-snapshot
So many states, so little time: verifying memory coherence in the Cray X1
inferredcites →https://doi.org/10.1109/isca.1994.288164openalex-snapshot
Evaluating stream buffers as a secondary cache replacement
inferredcites →https://doi.org/10.1109/isca.2002.1003586openalex-snapshot
Tarantula: a vector extension to the alpha architecture
inferredcites →https://doi.org/10.1109/isca.2004.1310763openalex-snapshot
The vector-thread architecture
inferredcites →https://doi.org/10.1109/micro.1997.645807openalex-snapshot
Out-of-order vector architectures
inferredcites →https://doi.org/10.1109/micro.2003.1253190openalex-snapshot
The reconfigurable streaming vector processor (RSVP/spl trade/)
inferredcites →https://doi.org/10.1109/mm.2003.1261383openalex-snapshot
Runahead execution: an effective alternative to large instruction windows
inferredcites →https://doi.org/10.1145/1028176.1006736openalex-snapshot
The Vector-Thread Architecture
inferredcites →https://doi.org/10.1145/1067649.801719openalex-snapshot
Decoupled access/execute computer architectures
inferredcites →https://doi.org/10.1145/115952.115959openalex-snapshot
Data prefetching in multiprocessor vector cache memories
inferredcites →https://doi.org/10.1145/125826.125932openalex-snapshot
An effective on-chip preloading scheme to reduce data access penalty
inferredcites →https://doi.org/10.1145/191995.192014openalex-snapshot
Evaluating stream buffers as a secondary cache replacement
inferredcites →https://doi.org/10.1145/2591635.2667173openalex-snapshot
Improving data cache performance by pre-executing instructions under a cache miss
inferredcites →https://doi.org/10.1145/263580.263597openalex-snapshot
Improving data cache performance by pre-executing instructions under a cache miss
inferredcites →https://doi.org/10.1145/264107.264208openalex-snapshot
Data prefetching on the HP PA-8000
inferredcites →https://doi.org/10.1145/285930.285979openalex-snapshot
Lockup-free instruction fetch/prefetch cache organization
inferredcites →https://doi.org/10.1145/285930.285998openalex-snapshot
Improving direct-mapped cache performance by the addition of a small fully-associative cache prefetch buffers
inferredcites →https://doi.org/10.1145/325164.325162openalex-snapshot
Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers
inferredcites →https://doi.org/10.1145/859618.859664openalex-snapshot
Overcoming the limitations of conventional vector processors
inferredcites →https://doi.org/10.1145/859662.859664openalex-snapshot
Overcoming the limitations of conventional vector processors
inferredcites →https://doi.org/10.5555/266800.266816openalex-snapshot
Out-of-order vector architectures
inferredcites →https://doi.org/10.5555/956417.956540openalex-snapshot
The Reconfigurable Streaming Vector Processor (RSVPTM)
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/s11227-026-08457-xopenalex-snapshot
Bicameral+ Cache: re-assessing split vector and scalar cache designs for increased efficiency
inferred← citeshttps://doi.org/10.1007/s11390-025-4555-4openalex-snapshot
Decoupled Vector Processing Unit: Past, Present, and Future
inferred← citeshttps://doi.org/10.1109/coolchips68842.2026.11557025openalex-snapshot
PRAVE: Partial Out-of-Order Execution for Superscalar Processors with Vector Extension
inferred← citeshttps://doi.org/10.1109/estimedia.2013.6704506openalex-snapshot
Design and evaluation of a media-oriented vector processor with a multi-banked cache memory
inferred← citeshttps://doi.org/10.1109/hpca.2005.10openalex-snapshot
Chip Multithreading: Opportunities and Challenges
inferred← citeshttps://doi.org/10.1109/ispa.2008.100openalex-snapshot
Effects of MSHR and Prefetch Mechanisms on an On-Chip Cache of the Vector Architecture
inferred← citeshttps://doi.org/10.1109/jssc.2016.2519386openalex-snapshot
A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC–DC Converters in 28 nm FDSOI
inferred← citeshttps://doi.org/10.1109/samos.2014.6893190openalex-snapshot
Dynamic-vector execution on a general purpose EDGE chip multiprocessor
inferred← citeshttps://doi.org/10.1109/sc.2006.62openalex-snapshot
The Potential Energy Efficiency of Vector Acceleration
inferred← citeshttps://doi.org/10.1145/1188455.1188537openalex-snapshot
Architecture---The potential energy efficiency of vector acceleration
inferred← citeshttps://doi.org/10.1145/1356058.1356085openalex-snapshot
Compiling for vector-thread architectures
inferred← citeshttps://doi.org/10.1145/1367045.1367050openalex-snapshot
Implementing the scale vector-thread processor
inferred← citeshttps://doi.org/10.1145/2000064.2000080openalex-snapshot
Exploring the tradeoffs between programmability and efficiency in data-parallel accelerators
inferred← citeshttps://doi.org/10.1145/2491464openalex-snapshot
Exploring the Tradeoffs between Programmability and Efficiency in Data-Parallel Accelerators
inferred← citeshttps://doi.org/10.1145/3466752.3480099openalex-snapshot
Software-Defined Vector Processing on Manycore Fabrics
inferred← citeshttps://doi.org/10.1587/transinf.2014edp7227openalex-snapshot
MVP-Cache: A Multi-Banked Cache Memory for Energy-Efficient Vector Processing of Multimedia Applications
inferred← citeshttps://doi.org/10.2200/s00647ed1v01y201505cac032openalex-snapshot
Single-Instruction Multiple-Data Execution
inferred← citeshttps://doi.org/10.5821/dissertation-2117-96236openalex-snapshot
Specialization and reconfiguration of lightweight mobile processors for data-parallel applications
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