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A Novel Architecture and Routing Algorithm for Dynamic Reconfigurable Network-on-Chip

https://doi.org/10.1109/ispa.2011.38
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Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1006/jpdc.2002.1837openalex-snapshot
Performance Tuning of Adaptive Wormhole Routing through Selection Function Choice
inferredcites →https://doi.org/10.1109/asscc.2006.357888openalex-snapshot
Design of a Dual-Mode NoC Router Integrated with Network Interface for AMBA-based IPs
inferredcites →https://doi.org/10.1109/l-ca.2007.2openalex-snapshot
Circuit-Switched Coherence
inferredcites →https://doi.org/10.1109/mdt.2005.99openalex-snapshot
Æthereal Network on Chip:Concepts, Architectures, and Implementations
inferredcites →https://doi.org/10.1109/nocs.2008.4492725openalex-snapshot
ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology
inferredcites →https://doi.org/10.1109/nocs.2008.4492738openalex-snapshot
Circuit-Switched Coherence
inferredcites →https://doi.org/10.1109/nocs.2009.5071468openalex-snapshot
Performance and power efficient on-chip communication using adaptive virtual point-to-point connections
inferredcites →https://doi.org/10.1109/tc.2008.38openalex-snapshot
Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip
inferredcites →https://doi.org/10.1145/139669.140384openalex-snapshot
The turn model for adaptive routing
inferredcites →https://doi.org/10.1145/285930.286003openalex-snapshot
The turn model for adaptive routing
inferredcites →https://doi.org/10.1145/378239.379048openalex-snapshot
Route packets, net wires

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-81-322-2247-7_25openalex-snapshot
Dynamic Reconfigurable Architectures—A Boon for Desires of Real Time Systems
inferred← citeshttps://doi.org/10.1016/j.sysarc.2014.10.002openalex-snapshot
MoNoC: A monitored network on chip with path adaptation mechanism
inferred← citeshttps://doi.org/10.1016/j.vlsi.2016.02.001openalex-snapshot
Bio-inspired NoC fault tolerant techniques using guaranteed throughput and best effort services
inferred← citeshttps://doi.org/10.1109/dsd53832.2021.00030openalex-snapshot
Architectural Implementation of a Reconfigurable NoC Design for Multi-Applications
inferred← citeshttps://doi.org/10.1109/icctct.2018.8551009openalex-snapshot
A Review on Hybrid Network on Chip
inferred← citeshttps://doi.org/10.1109/iraniancee.2014.6999671openalex-snapshot
A reconfigurable Network-on-Chip architecture to improve overall performance and throughput
inferred← citeshttps://doi.org/10.1109/isvdat.2014.6881041openalex-snapshot
A locally reconfigurable Network-on-Chip architecture and application mapping onto it
inferred← citeshttps://doi.org/10.1145/2556944openalex-snapshot
Multi-Application Network-on-Chip Design using Global Mapping and Local Reconfiguration
inferred← citeshttps://doi.org/10.1201/9781315216072openalex-snapshot
Network-on-Chip: The Next Generation of System-on-Chip Integration
inferred← citeshttps://doi.org/10.1201/9781315216072-10openalex-snapshot
Reconfigurable Network-on-Chip Design
inferred← citeshttps://doi.org/10.1201/b17748-11openalex-snapshot
Reconfigurable Network-on-Chip Design
inferred← citeshttps://doi.org/10.3390/mi14101913openalex-snapshot
Dynamically Scalable NoC Architecture for Implementing Run-Time Reconfigurable Applications
inferred← citeshttps://doi.org/10.70675/4aee6638zf3c5z44c2z95afza6cea3672b37openalex-snapshot
Run-time scalable NoC for virtualized FPGA based accelerators as cloud services
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