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Multi-Application Network-on-Chip Design using Global Mapping and Local Reconfiguration

https://doi.org/10.1145/2556944
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-3-642-12267-5_13openalex-snapshot
A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication
inferredcites →https://doi.org/10.1007/s11721-007-0002-0openalex-snapshot
Particle swarm optimization
inferredcites →https://doi.org/10.1016/j.micpro.2012.05.012openalex-snapshot
Design and evaluation of Mesh-of-Tree based Network-on-Chip using virtual channel router
inferredcites →https://doi.org/10.1016/j.micpro.2012.08.005openalex-snapshot
Mapping multiple applications with unbounded and bounded number of cores on many-core networks-on-chip
inferredcites →https://doi.org/10.1016/j.sysarc.2010.10.001openalex-snapshot
New heuristic algorithms for energy aware application mapping and routing on mesh-based NoCs
inferredcites →https://doi.org/10.1016/j.sysarc.2012.10.004openalex-snapshot
A survey on application mapping strategies for Network-on-Chip design
inferredcites →https://doi.org/10.1016/j.sysarc.2013.05.013openalex-snapshot
Application-Specific Network-on-Chip synthesis with flexible router Placement
inferredcites →https://doi.org/10.1016/j.vlsi.2007.12.002openalex-snapshot
Network-on-Chip design and synthesis outlook
inferredcites →https://doi.org/10.1049/ip-cdt:20045016openalex-snapshot
Topology adaptive network-on-chip design and implementation
inferredcites →https://doi.org/10.1109/ahs.2006.25openalex-snapshot
Architecture of a Dynamically Reconfigurable NoC for Adaptive Reconfigurable MPSoC
inferredcites →https://doi.org/10.1109/aina.2010.108openalex-snapshot
Hybrid Communication Reconfigurable Network on Chip for MPSoC
inferredcites →https://doi.org/10.1109/ccece.1995openalex-snapshot
Proceedings 1995 Canadian Conference on Electrical and Computer Engineering
inferredcites →https://doi.org/10.1109/ccece.2007.240openalex-snapshot
Introducing OperaNP: A Reconfigurable NoC-Based Platform
inferredcites →https://doi.org/10.1109/cecnet.2012.6201598openalex-snapshot
Configuring algorithm for reconfigurable Network-on-Chip architecture
inferredcites →https://doi.org/10.1109/date.2001openalex-snapshot
Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001
inferredcites →https://doi.org/10.1109/date.2005.137openalex-snapshot
Energy- and Performance-Driven NoC Communication Architecture Synthesis Using a Decomposition Approach
inferredcites →https://doi.org/10.1109/date.2006.243857openalex-snapshot
Application Specific NoC Design
inferredcites →https://doi.org/10.1109/date.2006.244007openalex-snapshot
A Methodology for Mapping Multiple Use-Cases onto Networks on Chips
inferredcites →https://doi.org/10.1109/eeei.2010.5662160openalex-snapshot
Multi-application mapping algorithm for Network-on-Chip platforms
inferredcites →https://doi.org/10.1109/iccd.2007.4601933openalex-snapshot
Power-aware mapping for reconfigurable NoC architectures
inferredcites →https://doi.org/10.1109/icinis.2008.100openalex-snapshot
Convergence Analysis of a Dynamic Discrete PSO Algorithm
inferredcites →https://doi.org/10.1109/icmlc.2003.1259748openalex-snapshot
Particle swarm optimization for traveling salesman problem
inferredcites →https://doi.org/10.1109/icmlc.2004.1378168openalex-snapshot
Proceedings of 2004 International Conference on Machine Learning and Cybernetics
inferredcites →https://doi.org/10.1109/ipdpsw.2010.5470753openalex-snapshot
A reconfigurable architecture for multicore systems
inferredcites →https://doi.org/10.1109/ispa.2011.38openalex-snapshot
A Novel Architecture and Routing Algorithm for Dynamic Reconfigurable Network-on-Chip
inferredcites →https://doi.org/10.1109/issoc.2003.1267722openalex-snapshot
Highly scalable network on chip for reconfigurable systems
inferredcites →https://doi.org/10.1109/nocs.2008.4492725openalex-snapshot
ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology
inferredcites →https://doi.org/10.1109/tcad.2005.844106openalex-snapshot
Energy- and performance-aware mapping for regular NoC architectures
inferredcites →https://doi.org/10.1109/tcad.2008.2003301openalex-snapshot
Energy- and Performance-Aware Incremental Mapping for Networks on Chip With Multiple Voltage Levels
inferredcites →https://doi.org/10.1109/tpds.2005.22openalex-snapshot
NoC synthesis flow for customized domain specific multiprocessor systems-on-chip
inferredcites →https://doi.org/10.1109/tvlsi.2003.820523openalex-snapshot
On-chip traffic modeling and synthesis for MPEG-2 video applications
inferredcites →https://doi.org/10.1109/tvlsi.2006.871762openalex-snapshot
Linear-programming-based techniques for synthesis of network-on-chip architectures
inferredcites →https://doi.org/10.1109/tvlsi.2008.2004592openalex-snapshot
Throughput-Oriented NoC Topology Generation and Analysis for High Performance SoCs
inferredcites →https://doi.org/10.1109/tvlsi.2010.2066586openalex-snapshot
Application-Aware Topology Reconfiguration for On-Chip Networks
inferredcites →https://doi.org/10.1109/tvlsi.2010.2091686openalex-snapshot
ORION 2.0: A Power-Area Simulator for Interconnection Networks
inferredcites →https://doi.org/10.1109/tvlsi.2013.2240708openalex-snapshot
Application Mapping Onto Mesh-Based Network-on-Chip Using Discrete Particle Swarm Optimization
inferredcites →https://doi.org/10.1145/1118299.1118344openalex-snapshot
Mapping and configuration methods for multi-use-case networks on chips
inferredcites →https://doi.org/10.1145/1736065.1736066openalex-snapshot
A power-aware mapping approach to map IP cores onto NoCs under bandwidth and latency constraints
inferredcites →https://doi.org/10.1145/1837274.1837316openalex-snapshot
An efficient dynamically reconfigurable on-chip network architecture
inferredcites →https://doi.org/10.1145/378239.379048openalex-snapshot
Route packets, net wires
inferredcites →https://doi.org/10.1504/ijhpsa.2008.021797openalex-snapshot
Network-on-chip architecture design based on mesh-of-tree deterministic routing topology
inferredcites →https://doi.org/10.4108/icst.nanonet2007.2148openalex-snapshot
Algorithm for the Choice of Topology in Reconfigurable On-Chip Networks with Real-Time Support
inferredcites →https://doi.org/10.5555/278241.278309openalex-snapshot
TGFF: task graphs for free
inferredcites →https://doi.org/10.5555/968879.969207openalex-snapshot
Bandwidth-constrained mapping of cores onto NoC architectures

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-031-21514-8_24openalex-snapshot
MANA:Multi-Application Mapping onto Mesh Network-on-Chip using ANN
inferred← citeshttps://doi.org/10.1007/978-3-319-16214-0_33openalex-snapshot
Partial Reconfiguration for Dynamic Mapping of Task Graphs onto 2D Mesh Platform
inferred← citeshttps://doi.org/10.1007/978-981-32-9767-8_37openalex-snapshot
Multi-application Based Fault-Tolerant Network-on-Chip Design for Mesh Topology Using Reconfigurable Architecture
inferred← citeshttps://doi.org/10.1007/s10617-017-9193-9openalex-snapshot
Optimal mapping of program overlays onto many-core platforms with limited memory capacity
inferred← citeshttps://doi.org/10.1016/j.memori.2023.100059openalex-snapshot
A performance-centric ML-based multi-application mapping technique for regular Network-on-Chip
inferred← citeshttps://doi.org/10.1109/dsd53832.2021.00030openalex-snapshot
Architectural Implementation of a Reconfigurable NoC Design for Multi-Applications
inferred← citeshttps://doi.org/10.1109/hpcs.2018.00096openalex-snapshot
Fault Tolerant Routing Methodology for Mesh-of-Tree based Network-on-Chips using Local Reconfiguration
inferred← citeshttps://doi.org/10.1109/tencon.2018.8650346openalex-snapshot
Fault-Tolerant Network-on-Chip Design for Mesh-of-Tree Topology Using Particle Swarm Optimization
inferred← citeshttps://doi.org/10.1109/vlsid.2019.00119openalex-snapshot
Multi-application Based Network-on-Chip Design for Mesh-of-Tree Topology Using Global Mapping and Reconfigurable Architecture
inferred← citeshttps://doi.org/10.1145/2660540.2660992openalex-snapshot
Self-Adaptive Network On Chips
inferred← citeshttps://doi.org/10.1145/3269983openalex-snapshot
Fault-Tolerant Network-on-Chip Design with Flexible Spare Core Placement
inferred← citeshttps://doi.org/10.1145/3408324openalex-snapshot
Adaptive Task Allocation and Scheduling on NoC-based Multicore Platforms with Multitasking Processors
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