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A Scalable NoC Router Design Providing QoS Support Using Weighted Round Robin Scheduling

https://doi.org/10.1109/ispa.2012.93

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

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Dynamic System Reconfiguration in Heterogeneous Platforms: The MORPHEUS Approach

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Globally Synchronized Frames for guaranteed quality-of-service in on-chip networks

inferredcites →https://doi.org/10.1016/j.micpro.2010.09.007openalex-snapshot

A TDM slot allocation flow based on multipath routing in NoCs

inferredcites →https://doi.org/10.1016/j.sysarc.2003.07.004openalex-snapshot

QNoC: QoS architecture and design process for network on chip

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Networks on chips: a new SoC paradigm

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Weighted round-robin cell multiplexing in a general-purpose ATM switch chip

inferredcites →https://doi.org/10.1109/apccas.2008.4746325openalex-snapshot

Dynamic TDM virtual circuit implementation for NoC

inferredcites →https://doi.org/10.1109/date.2004.1269001openalex-snapshot

Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip

inferredcites →https://doi.org/10.1109/date.2005.36openalex-snapshot

A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip

inferredcites →https://doi.org/10.1109/date.2009.5090821openalex-snapshot

In-network reorder buffer to improve overall NoC performance while resolving the in-order requirement problem

inferredcites →https://doi.org/10.1109/date.2010.5457213openalex-snapshot

Heterogeneous vs homogeneous MPSoC approaches for a Mobile LTE modem

inferredcites →https://doi.org/10.1109/estmed.2005.1518069openalex-snapshot

Dynamic time-slot allocation for QoS enabled networks on chip

inferredcites →https://doi.org/10.1109/iccd.2010.5647577openalex-snapshot

QoS scheduling for NoCs: Strict Priority Queueing versus Weighted Round Robin

inferredcites →https://doi.org/10.1109/icicdt.2010.5510291openalex-snapshot

MAGALI: A Network-on-Chip based multi-core system-on-chip for MIMO 4G SDR

inferredcites →https://doi.org/10.1109/ipdps.2010.5470359openalex-snapshot

QoS aware BiNoC architecture

inferredcites →https://doi.org/10.1109/ipdpsw.2012.25openalex-snapshot

Hardware-assisted Decentralized Resource Management for Networks on Chip with QoS

inferredcites →https://doi.org/10.1109/iscc.2000.860739openalex-snapshot

Managing performance using weighted round-robin

inferredcites →https://doi.org/10.1109/isscc.2010.5434077openalex-snapshot

A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS

inferredcites →https://doi.org/10.1109/issoc.2005.1595647openalex-snapshot

Overview of the 4S Project

inferredcites →https://doi.org/10.1109/jssc.2007.909339openalex-snapshot

A Reconfigurable Baseband Platform Based on an Asynchronous Network-on-Chip

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A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling

inferredcites →https://doi.org/10.1109/mdt.2005.99openalex-snapshot

Æthereal Network on Chip:Concepts, Architectures, and Implementations

inferredcites →https://doi.org/10.1109/tpds.2005.22openalex-snapshot

NoC synthesis flow for customized domain specific multiprocessor systems-on-chip

inferredcites →https://doi.org/10.1109/tvlsi.2008.2000673openalex-snapshot

TDM Virtual-Circuit Configuration for Network-on-Chip

inferredcites →https://doi.org/10.1145/1146909.1147124openalex-snapshot

A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip

inferredcites →https://doi.org/10.1145/1278480.1278667openalex-snapshot

Thousand core chips

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Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks

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Preemptive virtual clock

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Heterogeneous vs homogeneous MPSoC approaches for a mobile LTE modem

inferredcites →https://doi.org/10.5555/1874620.1874879openalex-snapshot

In-network reorder buffer to improve overall NoC performance while resolving the in-order requirement problem

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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The impact of formulation of cost function in Task Mapping Problem on NoCs using bio-inspired based-metaheuristics

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Heterogeneous Hardware Accelerators with Hybrid Interconnect: An Automated Design Approach

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Heterogeneous hardware accelerators interconnect: An overview

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Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study

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High-Level Synthesis in the Delft Workbench Hardware/Software Co-design Tool-Chain

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Theoretical Analysis and Evaluation of NoCs with Weighted Round-Robin Arbitration

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Rerouting: Scalable NoC self-optimization by distributed hardware-based connection reallocation

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Efficient memory access in 2D Mesh NoC architectures using high bandwidth routers

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Classified Round Robin: A Simple Prioritized Arbitration to Equip Best Effort NoCs With Effective Hard QoS

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NoC simulation in heterogeneous architectures for PGAS programming model

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CAP

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Age-aware Adaptive Routing for Network-on-Chip Routing with Odd-Even Turn Model

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