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A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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Principles of Asynchronous Circuit Design
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Networks on chips: a new SoC paradigm
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A delay model for router microarchitectures
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A global wiring paradigm for deep submicron design
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Globally-asynchronous locally-synchronous architectures to simplify the design of on-chip systems
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Delay insensitive system-on-chip interconnect using 1-of-4 data encoding
inferredcites →https://doi.org/10.1109/async.2005.7openalex-snapshot
A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip
inferredcites →https://doi.org/10.1109/date.2003.1253633openalex-snapshot
Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip
inferredcites →https://doi.org/10.1109/date.2004.1269001openalex-snapshot
Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip
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Low-latency virtual-channel routers for on-chip networks
inferredcites →https://doi.org/10.1109/norchp.2004.1423875openalex-snapshot
Virtual channel designs for guaranteeing bandwidth in asynchronous network-on-chip
inferredcites →https://doi.org/10.1109/socc.2004.1362432openalex-snapshot
An asynchronous on-chip network router with quality-of-service (QoS) support
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Low-Latency Virtual-Channel Routers for On-Chip Networks
inferredcites →https://doi.org/10.5555/789083.1022751openalex-snapshot
Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Impact of Message Based Fault Detectors on Applications Messages in a Network on Chip
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Hardware design and implementation of a Network-on-Chip based load balancing switch fabric
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A new mechanism to reduce congestion on TDM networks-on-chips
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Low overhead predictability enhancement in non-preemptive network-on-chip routers using Priority Forwarded Packet Splitting
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Programmable Switch for Shared Bus Replacement
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BaBaNoC: An asynchronous network-on-chip described in Balsa
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Dynamic Control for Mixed-Critical Networks-on-Chip
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Efficient memory access in 2D Mesh NoC architectures using high bandwidth routers
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An On-chip Switch Architecture for Hardware Accelerated Cloud Computing Systems
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A Compact and High Performance Switch for Circuit-Switched Network-On-Chip
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Building asynchronous routers with independent sub-channels
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High-performance adaption of ARM processors into Network-on-Chip architectures
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A novel flow fluidity meter for BiNoC bandwidth resource allocation
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A Buffered Crossbar-Based Chip Interconnection Architecture Supporting Quality of Service
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SD-MAC: Design and Synthesis of a Hardware-Efficient Collision-Free QoS-Aware MAC Protocol for Wireless Network-on-Chip
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Computing Accurate Performance Bounds for Best Effort Networks-on-Chip
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dAElite: A TDM NoC Supporting QoS, Multicast, and Fast Connection Set-Up
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MoDe-X: Microarchitecture of a Layout-Aware Modular Decoupled Crossbar for On-Chip Interconnects
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Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives
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Virtual Point-to-Point Connections for NoCs
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A Reconfigurable Source-Synchronous On-Chip Network for GALS Many-Core Platforms
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A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors
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Design of an Energy-Efficient Asynchronous NoC and Its Optimization Tools for Heterogeneous SoCs
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Application-Aware NoC Design for Efficient SDRAM Access
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Asynchronous Bypass Channels for Multi-Synchronous NoCs: A Router Microarchitecture, Topology, and Routing Algorithm
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Optimizing the NoC Slack Through Voltage and Frequency Scaling in Hard Real-Time Embedded Systems
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PhaseNoC: Versatile Network Traffic Isolation Through TDM-Scheduled Virtual Channels
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High Performance Dynamic Resource Allocation for Guaranteed Service in Network-on-Chips
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Contention-Aware Energy Management Scheme for NoC-Based Multicore Real-Time Systems
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MACS: A Highly Customizable Low-Latency Communication Architecture
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Survey on Real-Time Networks-on-Chip
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TDM Virtual-Circuit Configuration for Network-on-Chip
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Design and Management of Voltage-Frequency Island Partitioned Networks-on-Chip
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AFTER: Asynchronous Fault-Tolerant Router Design in Network-on-Chip
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COMMUNICATION MODELING OF QoS -AWARE WORMHOLE-ROUTED NoCs
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Key research problems in NoC design
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A survey of research and practices of Network-on-chip
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A buffered crossbar-based chip interconnection framework supporting quality of service
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Introducing the SuperGT network-on-chip
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Router architecture for high-performance NoCs
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A tool for automatic detection of deadlock in wormhole networks on chip
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Analysis and optimization of prediction-based flow control in networks-on-chip
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Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks
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Synthesis of topology configurations and deadlock free routing algorithms for ReNoC-based systems-on-chip
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Breaking adaptive multicast deadlock by virtual channel address/data FIFO decoupling
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