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Efficient Scheduling Algorithms for MpSoC Systems

https://doi.org/10.1109/itng.2011.121

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1016/b978-0-12-369485-0.x5000-3openalex-snapshot

High-Performance Embedded Computing

inferredcites →https://doi.org/10.1016/j.sysarc.2007.07.006openalex-snapshot

Designing efficient irregular networks for heterogeneous systems-on-chip

inferredcites →https://doi.org/10.1049/ip-cdt:20045092openalex-snapshot

Communication and task scheduling of application-specific networks-on-chip

inferredcites →https://doi.org/10.1109/date.2004.1269002openalex-snapshot

Bandwidth-constrained mapping of cores onto NoC architectures

inferredcites →https://doi.org/10.1109/dsd.2006.81openalex-snapshot

Resource-Efficient Routing and Scheduling of Time-Constrained Network-on-Chip Communication

inferredcites →https://doi.org/10.1109/iccad.2003.159732openalex-snapshot

Communication-aware task scheduling and voltage selection for total systems energy minimization

inferredcites →https://doi.org/10.1109/lpe.2001.945370openalex-snapshot

Hard real-time scheduling for low-energy using stochastic data and DVS processors

inferredcites →https://doi.org/10.1109/newcas.2008.4606313openalex-snapshot

A method for efficient mapping and reliable routing for NoC architectures with minimum bandwidth and area

inferredcites →https://doi.org/10.1109/pcee.2002.1115229openalex-snapshot

Real-time scheduling in distributed systems

inferredcites →https://doi.org/10.1109/rsp.2007.26openalex-snapshot

Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs

inferredcites →https://doi.org/10.1109/tcad.2005.844106openalex-snapshot

Energy- and performance-aware mapping for regular NoC architectures

inferredcites →https://doi.org/10.1109/tcad.2008.2010691openalex-snapshot

Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives

inferredcites →https://doi.org/10.1145/1016720.1016763openalex-snapshot

Power-aware communication optimization for networks-on-chips with voltage scalable links

inferredcites →https://doi.org/10.1145/1016720.1016765openalex-snapshot

Multi-objective mapping for mesh-based NoC architectures

inferredcites →https://doi.org/10.1145/1077603.1077695openalex-snapshot

A technique for low energy mapping and routing in network-on-chip architectures

inferredcites →https://doi.org/10.1145/1283780.1283828openalex-snapshot

Approximation algorithms for power minimization of earliest deadline first and rate monotonic schedules

inferredcites →https://doi.org/10.1145/383082.383092openalex-snapshot

Hard real-time scheduling for low-energy using stochastic data and DVS processors

inferredcites →https://doi.org/10.1145/972627.972636openalex-snapshot

Iterative schedule optimization for voltage scalable distributed embedded systems

inferredcites →https://doi.org/10.5555/1266366.1266390openalex-snapshot

An ILP formulation for system-level application mapping on network processor architectures

inferredcites →https://doi.org/10.5555/968879.969207openalex-snapshot

Bandwidth-constrained mapping of cores onto NoC architectures

inferredcites →https://doi.org/10.5555/996070.1009938openalex-snapshot

Communication-Aware Task Scheduling and Voltage Selection for Total Systems Energy Minimization

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/s10617-018-9208-1openalex-snapshot

ImGA: an improved genetic algorithm for partitioned scheduling on heterogeneous multi-core systems

inferred← citeshttps://doi.org/10.1109/acssc.2012.6489267openalex-snapshot

Partitioning and mapping dynamic dataflow programs

inferred← citeshttps://doi.org/10.1109/confluence.2017.7943197openalex-snapshot

3D implementation of heterogeneous topologies on MPSoC

inferred← citeshttps://doi.org/10.1109/icecs.2015.7440310openalex-snapshot

A hierarchical LST-based task scheduler for NoC-based MPSoCs with slack-time monitoring support

inferred← citeshttps://doi.org/10.1109/icsess.2018.8663813openalex-snapshot

Traffic-Aware and Memory-Aware Task Scheduling on Multi-Core Chips

inferred← citeshttps://doi.org/10.1109/mcsoc.2016.25openalex-snapshot

Design Space Exploration Problem Formulation for Dataflow Programs on Heterogeneous Architectures

inferred← citeshttps://doi.org/10.1145/2902961.2903027openalex-snapshot

Dynamic Real-Time Scheduler for Large-Scale MPSoCs

inferred← citeshttps://doi.org/10.1145/2990299.2990319openalex-snapshot

Schedulability-guided exploration of multi-core systems

inferred← citeshttps://doi.org/10.15446/dyna.v81n185.34867openalex-snapshot

Static and dynamic task mapping onto network on chip multiprocessors

inferred← citeshttps://doi.org/10.70675/7b4aff50z7e9dz4b1ez9e6ez9043a5ba7cb4openalex-snapshot

Towards Efficient Reuse of Software Programmable Streaming Coarse Grained Reconfigurable Architectures

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