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Resource-Efficient Routing and Scheduling of Time-Constrained Network-on-Chip Communication
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-3-540-30113-4_7openalex-snapshot
Predictable Embedded Multiprocessor System Design
inferredcites →https://doi.org/10.1049/ip-cdt:20030830openalex-snapshot
Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip
inferredcites →https://doi.org/10.1049/ip-cdt:20045092openalex-snapshot
Communication and task scheduling of application-specific networks-on-chip
inferredcites →https://doi.org/10.1109/2.976921openalex-snapshot
Networks on chips: a new SoC paradigm
inferredcites →https://doi.org/10.1109/4.826824openalex-snapshot
A single-chip, 1.6-billion, 16-b MAC/s multiprocessor DSP
inferredcites →https://doi.org/10.1109/date.2004.1269001openalex-snapshot
Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip
inferredcites →https://doi.org/10.1109/date.2004.1269203openalex-snapshot
Application of a multi-processor SoC platform to high-speed packet forwarding
inferredcites →https://doi.org/10.1109/date.2005.11openalex-snapshot
A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification
inferredcites →https://doi.org/10.1109/date.2006.244007openalex-snapshot
A Methodology for Mapping Multiple Use-Cases onto Networks on Chips
inferredcites →https://doi.org/10.1109/mcc.1999.766975openalex-snapshot
Parallel Computer Architecture: A Hardware/Software Approach
inferredcites →https://doi.org/10.1109/mdt.2002.1018132openalex-snapshot
A heterogeneous multiprocessor architecture for flexible media processing
inferredcites →https://doi.org/10.1145/1084834.1084857openalex-snapshot
A unified approach to constrained mapping and routing on network-on-chip architectures
inferredcites →https://doi.org/10.1145/139669.140384openalex-snapshot
The turn model for adaptive routing
inferredcites →https://doi.org/10.1145/146628.140384openalex-snapshot
The turn model for adaptive routing
inferredcites →https://doi.org/10.5555/789083.1022751openalex-snapshot
Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1016/j.sysarc.2007.07.004openalex-snapshot
Resource-efficient routing and scheduling of time-constrained streaming communication on networks-on-chip
inferred← citeshttps://doi.org/10.1016/j.sysarc.2012.10.004openalex-snapshot
A survey on application mapping strategies for Network-on-Chip design
inferred← citeshttps://doi.org/10.1109/ddecs.2011.5783086openalex-snapshot
Communication modelling and synthesis for NoC-based systems with real-time constraints
inferred← citeshttps://doi.org/10.1109/dsd.2009.195openalex-snapshot
Exploration of Slot Allocation for On-Chip TDM Virtual Circuits
inferred← citeshttps://doi.org/10.1109/iccad.2007.4397238openalex-snapshot
Slot allocation using logical networks for TDM virtual-circuit configuration for network-on-chip
inferred← citeshttps://doi.org/10.1109/iccd.2010.5647577openalex-snapshot
QoS scheduling for NoCs: Strict Priority Queueing versus Weighted Round Robin
inferred← citeshttps://doi.org/10.1109/iccd.2013.6657088openalex-snapshot
Resource allocation algorithms for guaranteed service in application-specific NoCs
inferred← citeshttps://doi.org/10.1109/itng.2011.121openalex-snapshot
Efficient Scheduling Algorithms for MpSoC Systems
inferred← citeshttps://doi.org/10.1109/socc.2009.5335670openalex-snapshot
Scheduling framework for real-time dependable NoC-based systems
inferred← citeshttps://doi.org/10.1109/tvlsi.2008.2000673openalex-snapshot
TDM Virtual-Circuit Configuration for Network-on-Chip
inferred← citeshttps://doi.org/10.1145/2567936openalex-snapshot
Post-silicon platform for the functional diagnosis and debug of networks-on-chip
inferred← citeshttps://doi.org/10.1145/2834848.2834851openalex-snapshot
Flexible TDM-based resource management in on-chip networks
inferred← citeshttps://doi.org/10.1145/2892633openalex-snapshot
Dynamic Task Mapping with Congestion Speculation for Reconfigurable Network-on-Chip
inferred← citeshttps://doi.org/10.1155/2007/68432openalex-snapshot
A Unified Approach to Mapping and Routing on a Network-on-Chip for Both Best-Effort and Guaranteed Service Traffic
inferred← citeshttps://doi.org/10.1155/2013/936181openalex-snapshot
Framework for Simulation of Heterogeneous MpSoC for Design Space Exploration
inferred← citeshttps://doi.org/10.4018/978-1-4666-5125-8.ch020openalex-snapshot
System-Level Design of NoC-Based Dependable Embedded Systems
inferred← citeshttps://doi.org/10.4018/978-1-60960-212-3.ch001openalex-snapshot
System-Level Design of NoC-Based Dependable Embedded Systems
inferred← citeshttps://doi.org/10.5555/1326073.1326079openalex-snapshot
Slot allocation using logical networks for TDM virtual-circuit configuration for network-on-chip
inferred← citeshttps://doi.org/10.6100/ir635718openalex-snapshot
Timing analysis of synchronous data flow graphs
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