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UNPU: An Energy-Efficient Deep Neural Network Accelerator With Fully Variable Weight Bit Precision
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Outgoing claims: the papers this work cites, builds on, or argues with.
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Quantized Convolutional Neural Networks for Mobile Devices
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DeepX: A Software Accelerator for Low-Power Deep Learning Inference on Mobile Devices
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14.6 A 1.42TOPS/W deep convolutional neural network recognition processor for intelligent IoE systems
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14.1 A 2.9TOPS/W deep convolutional neural network SoC in FD-SOI 28nm for intelligent embedded systems
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14.2 DNPU: An 8.1TOPS/W reconfigurable CNN-RNN processor for general-purpose deep neural networks
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14.3 A 28nm SoC with a 1.2GHz 568nJ/prediction sparse deep-neural-network engine with >0.1 timing error rate tolerance for IoT applications
inferredcites →https://doi.org/10.1109/isscc.2017.7870353openalex-snapshot
14.5 Envision: A 0.26-to-10TOPS/W subword-parallel dynamic-voltage-accuracy-frequency-scalable Convolutional Neural Network processor in 28nm FDSOI
inferredcites →https://doi.org/10.1109/isscc.2018.8310261openalex-snapshot
QUEST: A 7.49TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS
inferredcites →https://doi.org/10.1109/isscc.2018.8310262openalex-snapshot
UNPU: A 50.6TOPS/W unified deep neural network accelerator with 1b-to-16b fully-variable weight bit-precision
inferredcites →https://doi.org/10.1109/jssc.2016.2616357openalex-snapshot
Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks
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A Low-Power Convolutional Neural Network Face Recognition Processor and a CIS Integrated With Always-on Face Detector
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Stripes: Bit-serial deep neural network computing
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A 0.3–2.6 TOPS/W precision-scalable processor for real-time large-scale ConvNets
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In-Datacenter Performance Analysis of a Tensor Processing Unit
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In-Datacenter Performance Analysis of a Tensor Processing Unit
inferredcites →https://doi.org/10.1609/aaai.v32i1.11876openalex-snapshot
DeepRebirth: Accelerating Deep Neural Network Execution on Mobile Devices
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BRein memory: A 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS
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Compression of Deep Convolutional Neural Networks for Fast and Low Power Mobile Applications
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DeepSense: A Unified Deep Learning Framework for Time-Series Mobile Sensing Data Processing
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Effective Quantization Methods for Recurrent Neural Networks
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Trained Ternary Quantization
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fpgaConvNet: A Toolflow for Mapping Diverse Convolutional Neural Networks on Embedded FPGAs
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High performance ultra-low-precision convolutions on mobile devices
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inferred← citeshttps://doi.org/10.2139/ssrn.4141234openalex-extracted
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inferred← citeshttps://doi.org/10.1109/asap.2019.000-9openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/cstic52283.2021.9461576openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/essderc53440.2021.9631821openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/hpca53966.2022.00068openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/ieeeconf51394.2020.9443508openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/ipdpsw50202.2020.00142openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/isca52012.2021.00072openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/isca59077.2024.00016openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/isca66397.2026.00037openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/iscas.2019.8702243openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/iscas45731.2020.9180844openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/iscas46773.2023.10181612openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/iscas48785.2022.9937290openalex-snapshot
Histogram-Equalized Quantization for logic-gated Residual Neural Networks
inferred← citeshttps://doi.org/10.1109/iscas48785.2022.9937753openalex-snapshot
A Reconfigurable Depth-Wise Convolution Module for Heterogeneously Quantized DNNs
inferred← citeshttps://doi.org/10.1109/iscas48785.2022.9937946openalex-snapshot
Dynamically Swappable Digit-Serial Multi-Precision Deep Neural Network Accelerator with Early Termination
inferred← citeshttps://doi.org/10.1109/iscas51556.2021.9401206openalex-snapshot
A 3.6 TOPS/W Hybrid FP-FXP Deep Learning Processor with Outlier Compensation for Image-to-Image Application
inferred← citeshttps://doi.org/10.1109/iscas51556.2021.9401214openalex-snapshot
ChewBaccaNN: A Flexible 223 TOPS/W BNN Accelerator
inferred← citeshttps://doi.org/10.1109/iscas51556.2021.9401475openalex-snapshot
Comparison of Digit-Serial and Bit-Level Designs for Acceleration of Convolutional Neural Network Computation
inferred← citeshttps://doi.org/10.1109/iscas51556.2021.9401657openalex-snapshot
Adaptive Quantization Method for CNN with Computational-Complexity-Aware Regularization
inferred← citeshttps://doi.org/10.1109/iscas56072.2025.11043465openalex-snapshot
A Flexible Precision Scaling Deep Neural Network Accelerator with Efficient Weight Combination
inferred← citeshttps://doi.org/10.1109/iscas56072.2025.11043563openalex-snapshot
DPD-NeuralEngine: A 22-nm 6.6-TOPS/W/mm2 Recurrent Neural Network Accelerator for Wideband Power Amplifier Digital Pre-Distortion
inferred← citeshttps://doi.org/10.1109/iscas56072.2025.11043759openalex-snapshot
High Energy Efficiency Spatial Parallel Stochastic Computing for Precision Scalable Neural Processing Unit
inferred← citeshttps://doi.org/10.1109/iscas58744.2024.10558398openalex-snapshot
A Precision-Scalable Vision Accelerator for Robotic Applications
inferred← citeshttps://doi.org/10.1109/iscas58744.2024.10558491openalex-snapshot
Neural Network Acceleration Using Digit-Plane Computation with Early Termination
inferred← citeshttps://doi.org/10.1109/iscas58744.2024.10558587openalex-snapshot
Enabling Efficient Hardware Acceleration of Hybrid Vision Transformer (ViT) Networks at the Edge
inferred← citeshttps://doi.org/10.1109/iscas58744.2024.10558641openalex-snapshot
Low-latency Buffering for Mixed-precision Neural Network Accelerator with MulTAP and FQPipe
inferred← citeshttps://doi.org/10.1109/iscas66217.2026.11562006openalex-snapshot
MEGA.mini-S: A 1.9-to-15.0 TOPS/W Generative AI Processor with Bit-serial Weight Scalability and Bank-Conflict-free Sparsity Compression
inferred← citeshttps://doi.org/10.1109/iscas66217.2026.11562908openalex-snapshot
PIM-NoC: A NoC Architecture with In-Router Processing-in-Memory for DNN Acceleration
inferred← citeshttps://doi.org/10.1109/iseda65950.2025.11100318openalex-snapshot
CIR-NoC: Accelerating CNN Inference Through In-Router Computation During Network Congestion
inferred← citeshttps://doi.org/10.1109/iseda65950.2025.11100582openalex-snapshot
MULiN: A NoC-DNN Accelerator Based on In-Network Multiplication
inferred← citeshttps://doi.org/10.1109/islped58423.2023.10244499openalex-snapshot
LAXOR: A Bit-Accurate BNN Accelerator with Latch-XOR Logic for Local Computing
inferred← citeshttps://doi.org/10.1109/isocc47750.2019.9078506openalex-snapshot
Scaling Bit-Flexible Neural Networks
inferred← citeshttps://doi.org/10.1109/ispa67752.2025.00020openalex-snapshot
QVU: A RISC-V Vector-Extended Quantization Vector Unit for IEEE 754 and Posit Formats
inferred← citeshttps://doi.org/10.1109/isqed54688.2022.9806248openalex-snapshot
Design and Challenges of Edge Computing ASICs on Front-End Electronics
inferred← citeshttps://doi.org/10.1109/isqed60706.2024.10528758openalex-snapshot
A SIMD Dynamic Fixed Point Processing Engine for DNN Accelerators
inferred← citeshttps://doi.org/10.1109/jetcas.2019.2911899openalex-snapshot
Low-Power Computer Vision: Status, Challenges, and Opportunities
inferred← citeshttps://doi.org/10.1109/jetcas.2019.2914355openalex-snapshot
iFPNA: A Flexible and Efficient Deep Learning Processor in 28-nm CMOS Using a Domain-Specific Instruction Set and Reconfigurable Fabric
inferred← citeshttps://doi.org/10.1109/jetcas.2019.2933148openalex-snapshot
Impact of Non-Ideal Characteristics of Resistive Synaptic Devices on Implementing Convolutional Neural Networks
inferred← citeshttps://doi.org/10.1109/jetcas.2019.2952137openalex-snapshot
Memory-Reduced Network Stacking for Edge-Level CNN Architecture With Structured Weight Pruning
inferred← citeshttps://doi.org/10.1109/jetcas.2020.3014454openalex-snapshot
SRNPU: An Energy-Efficient CNN-Based Super-Resolution Processor With Tile-Based Selective Super-Resolution in Mobile Devices
inferred← citeshttps://doi.org/10.1109/jetcas.2020.3015238openalex-snapshot
Design of a Sparsity-Aware Reconfigurable Deep Learning Accelerator Supporting Various Types of Operations
inferred← citeshttps://doi.org/10.1109/jetcas.2021.3125399openalex-snapshot
A Lego-Based Neural Network Design Methodology With Flexible NoC
inferred← citeshttps://doi.org/10.1109/jetcas.2022.3168852openalex-snapshot
Design of Processing-in-Memory With Triple Computational Path and Sparsity Handling for Energy-Efficient DNN Training
inferred← citeshttps://doi.org/10.1109/jetcas.2022.3170152openalex-snapshot
A Heterogeneous In-Memory Computing Cluster for Flexible End-to-End Inference of Real-World Deep Neural Networks
inferred← citeshttps://doi.org/10.1109/jetcas.2022.3172170openalex-snapshot
Parasitic-Aware Modeling and Neural Network Training Scheme for Energy-Efficient Processing-in-Memory With Resistive Crossbar Array
inferred← citeshttps://doi.org/10.1109/jetcas.2022.3214334openalex-snapshot
A Non-Idealities Aware Software–Hardware Co-Design Framework for Edge-AI Deep Neural Network Implemented on Memristive Crossbar
inferred← citeshttps://doi.org/10.1109/jproc.2020.2976475openalex-snapshot
Model Compression and Hardware Acceleration for Neural Networks: A Comprehensive Survey
inferred← citeshttps://doi.org/10.1109/jproc.2021.3098483openalex-snapshot
Hardware Acceleration of Sparse and Irregular Tensor Computations of ML Models: A Survey and Insights
inferred← citeshttps://doi.org/10.1109/jsen.2021.3070803openalex-snapshot
Adaptive Camera Platform Using Deep Learning-Based Early Warning of Task Failures
inferred← citeshttps://doi.org/10.1109/jssc.2019.2939682openalex-snapshot
A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing
inferred← citeshttps://doi.org/10.1109/jssc.2020.3005786openalex-snapshot
An Energy-Efficient Deep Convolutional Neural Network Training Accelerator for In Situ Personalization on Smart Devices
inferred← citeshttps://doi.org/10.1109/jssc.2020.3029235openalex-snapshot
An Energy-Efficient Deep Convolutional Neural Network Accelerator Featuring Conditional Computing and Low External Memory Access
inferred← citeshttps://doi.org/10.1109/jssc.2020.3038616openalex-snapshot
A 617-TOPS/W All-Digital Binary Neural Network Accelerator in 10-nm FinFET CMOS
inferred← citeshttps://doi.org/10.1109/jssc.2020.3039206openalex-snapshot
Z-PIM: A Sparsity-Aware Processing-in-Memory Architecture With Fully Variable Weight Bit-Precision for Energy-Efficient Deep Neural Networks
inferred← citeshttps://doi.org/10.1109/jssc.2020.3041502openalex-snapshot
COMPAC: Compressed Time-Domain, Pooling-Aware Convolution CNN Engine With Reduced Data Movement for Energy-Efficient AI Computing
inferred← citeshttps://doi.org/10.1109/jssc.2020.3043870openalex-snapshot
SNAP: An Efficient Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference
inferred← citeshttps://doi.org/10.1109/jssc.2021.3061508openalex-snapshot
Colonnade: A Reconfigurable SRAM-Based Digital Bit-Serial Compute-In-Memory Macro for Processing Neural Networks
inferred← citeshttps://doi.org/10.1109/jssc.2021.3090864openalex-snapshot
A Pipelined Point Cloud Based Neural Network Processor for 3-D Vision With Large-Scale Max Pooling Layer Prediction
inferred← citeshttps://doi.org/10.1109/jssc.2021.3095232openalex-snapshot
TIMAQ: A Time-Domain Computing-in-Memory-Based Processor Using Predictable Decomposed Convolution for Arbitrary Quantized DNNs
inferred← citeshttps://doi.org/10.1109/jssc.2021.3115466openalex-snapshot
SMIV: A 16-nm 25-mm² SoC for IoT With Arm Cortex-A53, eFPGA, and Coherent Accelerators
inferred← citeshttps://doi.org/10.1109/jssc.2022.3141050openalex-snapshot
BitBlade: Energy-Efficient Variable Bit-Precision Hardware Accelerator for Quantized Neural Networks
inferred← citeshttps://doi.org/10.1109/jssc.2022.3159473openalex-snapshot
A 65 nm Wireless Image SoC Supporting On-Chip DNN Optimization and Real-Time Computation-Communication Trade-Off via Actor-Critical Neuro-Controller
inferred← citeshttps://doi.org/10.1109/jssc.2022.3179601openalex-snapshot
A 184-μW Error-Tolerant Real-Time Hand Gesture Recognition System With Hybrid Tiny Classifiers Utilizing Edge CNN
inferred← citeshttps://doi.org/10.1109/jssc.2022.3214170openalex-snapshot
A Systolic Neural CPU Processor Combining Deep Learning and General-Purpose Computing With Enhanced Data Locality and End-to-End Performance
inferred← citeshttps://doi.org/10.1109/jssc.2022.3224964openalex-snapshot
An Efficient Deep-Learning-Based Super-Resolution Accelerating SoC With Heterogeneous Accelerating and Hierarchical Cache
inferred← citeshttps://doi.org/10.1109/jssc.2022.3228765openalex-snapshot
An Eight-Core RISC-V Processor With Compute Near Last Level Cache in Intel 4 CMOS
inferred← citeshttps://doi.org/10.1109/jssc.2023.3236566openalex-snapshot
TinyVers: A Tiny Versatile System-on-Chip With State-Retentive eMRAM for ML Inference at the Extreme Edge
inferred← citeshttps://doi.org/10.1109/jssc.2023.3312615openalex-snapshot
Multipurpose Deep-Learning Accelerator for Arbitrary Quantization With Reduction of Storage, Logic, and Latency Waste
inferred← citeshttps://doi.org/10.1109/jssc.2023.3319962openalex-snapshot
DynaPlasia: An eDRAM In-Memory Computing-Based Reconfigurable Spatial Accelerator With Triple-Mode Cell
inferred← citeshttps://doi.org/10.1109/jssc.2024.3362699openalex-snapshot
Scaling-CIM: eDRAM In-Memory-Computing Accelerator With Dynamic-Scaling ADC and Adaptive Analog Operation
inferred← citeshttps://doi.org/10.1109/jssc.2024.3377292openalex-snapshot
A Dynamic Execution Neural Network Processor for Fine-Grained Mixed-Precision Model Training Based on Online Quantization Sensitivity Analysis
inferred← citeshttps://doi.org/10.1109/jssc.2024.3386878openalex-snapshot
A 28-nm Energy-Efficient Sparse Neural Network Processor for Point Cloud Applications Using Block-Wise Online Neighbor Searching
inferred← citeshttps://doi.org/10.1109/jssc.2024.3453114openalex-snapshot
A 65 nm General-Purpose Compute-in-Memory Processor Supporting Both General Programming and Deep Learning Tasks
inferred← citeshttps://doi.org/10.1109/jssc.2024.3514733openalex-snapshot
A Scalable BEV Perception Processor for Image/Point Cloud Fusion Applications Using CAM-Based Universal Mapping Unit
inferred← citeshttps://doi.org/10.1109/jssc.2025.3532544openalex-snapshot
An 800-MHz 8.17-TOPS/W 0.63-TOPS/mm 2 Memory-Utilization-Aware CNN Accelerator Featuring a Memory Stationary Dataflow
inferred← citeshttps://doi.org/10.1109/jssc.2025.3558287openalex-snapshot
A 29.12-TOPS/W Vector Systolic Accelerator With NAS-Optimized DNNs in 28-nm CMOS
inferred← citeshttps://doi.org/10.1109/jssc.2025.3595012openalex-snapshot
An Area-Efficient Lookup-Table -Based eDRAM Digital CIM Macro for Neural Network Inference
inferred← citeshttps://doi.org/10.1109/jssc.2025.3639446openalex-snapshot
An Electrophysiology-Optogenetics Closed-Loop Bi-Directional Neural Interface for Sleep Regulation With 0.2-μJ/class Multiplexer-Based Neural Network
inferred← citeshttps://doi.org/10.1109/jxcdc.2020.2999581openalex-snapshot
aCortex: An Energy-Efficient Multipurpose Mixed-Signal Inference Accelerator
inferred← citeshttps://doi.org/10.1109/led.2020.3025587openalex-snapshot
AND Flash Array Based on Charge Trap Flash for Implementation of Convolutional Neural Networks
inferred← citeshttps://doi.org/10.1109/lssc.2020.3007185openalex-snapshot
A 2.9–33.0 TOPS/W Reconfigurable 1-D/2-D Compute-Near-Memory Inference Accelerator in 10-nm FinFET CMOS
inferred← citeshttps://doi.org/10.1109/lssc.2023.3286698openalex-snapshot
VideoTime3: A 40-uJ/frame 38 FPS Video Understanding Accelerator With Real-Time DiffFrame Temporal Redundancy Reduction and Temporal Modeling
inferred← citeshttps://doi.org/10.1109/mcsoc51149.2021.00024openalex-snapshot
Variable Bit-Precision Vector Extension for RISC-V Based Processors
inferred← citeshttps://doi.org/10.1109/mcsoc57363.2022.00043openalex-snapshot
Hardware characterization of Integer-Net based seizure detection models on FPGA
inferred← citeshttps://doi.org/10.1109/mdat.2022.3161126openalex-snapshot
A Survey on Machine Learning Accelerators and Evolutionary Hardware Platforms
inferred← citeshttps://doi.org/10.1109/micro56248.2022.00097openalex-snapshot
Ristretto: An Atomized Processing Architecture for Sparsity-Condensed Stream Flow in CNN
inferred← citeshttps://doi.org/10.1109/mssc.2022.3182935openalex-snapshot
Digital Versus Analog Artificial Intelligence Accelerators: Advances, trends, and emerging designs
inferred← citeshttps://doi.org/10.1109/mwscas47672.2021.9531720openalex-snapshot
An Arbitrary Kernel-size Applicable NoC-based DNN Processor Design with Hybrid Data Reuse
inferred← citeshttps://doi.org/10.1109/mwscas47672.2021.9531722openalex-snapshot
A Multi-Precision Bit-Serial Hardware Accelerator IP for Deep Learning Enabled Internet-of-Things
inferred← citeshttps://doi.org/10.1109/mwscas48704.2020.9184599openalex-snapshot
MSB-First Distributed Arithmetic Circuit for Convolution Neural Network Computation
inferred← citeshttps://doi.org/10.1109/mwscas53549.2025.11244482openalex-snapshot
MAKAN: Memristive Accelerated Kolmugruv-Arnold Networks
inferred← citeshttps://doi.org/10.1109/nocarc57472.2022.9911283openalex-snapshot
A Reconfigurable Deep Neural Network on Chip Design with Flexible Convolutional Operations
inferred← citeshttps://doi.org/10.1109/ojsscs.2021.3119554openalex-snapshot
An Overview of Energy-Efficient Hardware Accelerators for On-Device Deep-Neural-Network Training
inferred← citeshttps://doi.org/10.1109/prai67447.2025.11412639openalex-snapshot
Design of an Energy-Efficient Hybrid-Precision Neural Network Accelerator with a Unified Memory-Compute Architecture
inferred← citeshttps://doi.org/10.1109/socc52499.2021.9739237openalex-snapshot
A Convolutional Neural Network on Chip Design Methodology for CNN Hardware Implementation
inferred← citeshttps://doi.org/10.1109/socc58585.2023.10256738openalex-snapshot
Leveraging Mixed-Precision CNN Inference for Increased Robustness and Energy Efficiency
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