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Laser Annealing of Amorphous Germanium on Silicon–Germanium Source/Drain for Strain and Performance Enhancement in pMOSFETs
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1063/1.105085openalex-snapshot
Demonstration of laser-assisted epitaxial deposition of GexSi1−x alloys on single-crystal Si
inferredcites →https://doi.org/10.1063/1.107793openalex-snapshot
Crystallinity, strain, and thermal stability of heteroepitaxial Si1−xGex/Si (100) layers created using pulsed laser induced epitaxy
inferredcites →https://doi.org/10.1063/1.117620openalex-snapshot
Synthesis of SiGe and SiGeC alloys formed by Ge and C implantation
inferredcites →https://doi.org/10.1063/1.1395352openalex-snapshot
Strain measurements of semiconductor multilayers by ion channeling, high resolution XRD and Raman spectroscopy
inferredcites →https://doi.org/10.1063/1.1846152openalex-snapshot
Finite-element study of strain distribution in transistor with silicon–germanium source and drain regions
inferredcites →https://doi.org/10.1063/1.1871351openalex-snapshot
Lattice strain analysis of transistor structures with silicon–germanium and silicon–carbon source∕drain stressors
inferredcites →https://doi.org/10.1063/1.365793openalex-snapshot
X-ray diffraction and x-ray photoelectron spectroscopy study of partially strained SiGe layers produced via excimer laser processing
inferredcites →https://doi.org/10.1063/1.99528openalex-snapshot
Epitaxial GexSi1−x/Si (100) structures produced by pulsed laser mixing of evaporated Ge on Si (100) substrates
inferredcites →https://doi.org/10.1109/16.784194openalex-snapshot
A total resistance slope-based effective channel mobility extraction method for deep submicrometer CMOS technology
inferredcites →https://doi.org/10.1109/iedm.2003.1269442openalex-snapshot
A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors
inferredcites →https://doi.org/10.1109/iedm.2005.1609500openalex-snapshot
Demonstration of recessed SiGe S/D and inserted metal gate on HfO/sub 2/ for high performance pFETs.
inferredcites →https://doi.org/10.1109/iedm.2006.346958openalex-snapshot
Novel Enhanced Stressor with Graded Embedded SiGe Source/Drain for High Performance CMOS Devices
inferredcites →https://doi.org/10.1109/iedm.2007.4418923openalex-snapshot
High-Performance 45nm node CMOS Transistors Featuring Flash Lamp Annealing (FLA)
inferredcites →https://doi.org/10.1143/jjap.46.2058openalex-snapshot
Sub-30 nm Strained p-Channel Fin-Type Field-Effect Transistors with Condensed SiGe Source/Drain Stressors
inferredcites →https://doi.org/10.7567/ssdm.2006.h-1-4openalex-snapshot
Sub-30 nm Strained P-Channel FinFETs with Condensed SiGe Source/Drain Stressors
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.2139/ssrn.4142099openalex-extracted
An Emerging Local Annealing Method for Simultaneous Crystallization and Activation in Three-Dimensional Nand Flash
inferred← citeshttps://doi.org/10.1007/s11432-009-0167-9openalex-snapshot
Challenges of 22 nm and beyond CMOS technology
inferred← citeshttps://doi.org/10.1016/j.tsf.2010.07.104openalex-snapshot
Challenges to quantitative energy-dispersive X-ray spectrometry and its application to graded embedded silicon–germanium for high-performance complementary metal oxide semiconductor devices
inferred← citeshttps://doi.org/10.1049/iet-com.2016.1012openalex-snapshot
VFF ‐norm penalised WL‐RLS algorithm using DCD iterations for underwater acoustic communication
inferred← citeshttps://doi.org/10.1063/1.4714768openalex-snapshot
Silicon germanium tin alloys formed by pulsed laser induced epitaxy
inferred← citeshttps://doi.org/10.1109/led.2008.2010723openalex-snapshot
Performance Benefits of Diamond-like Carbon Liner Stressor in Strained P-Channel Field-Effect Transistors With Silicon–Germanium Source and Drain
inferred← citeshttps://doi.org/10.1109/led.2010.2063692openalex-snapshot
Gate-First $\hbox{TaN/La}_{2}\hbox{O}_{3}/ \hbox{SiO}_{2}/\hbox{Ge}$ n-MOSFETs Using Laser Annealing
inferred← citeshttps://doi.org/10.1109/led.2011.2106478openalex-snapshot
Higher Gate Capacitance Ge n-MOSFETs Using Laser Annealing
inferred← citeshttps://doi.org/10.1109/tsm.2022.3229471openalex-snapshot
An Emerging Local Annealing Method for Simultaneous Crystallization and Activation in Xtacking 3-D NAND Flash
inferred← citeshttps://doi.org/10.1143/jjap.49.060221openalex-snapshot
Investigation of Spacer Engineering on n-Type Field Effect Transistor Performance during Laser Spike Annealing
inferred← citeshttps://doi.org/10.23919/sispad49475.2020.9241664openalex-snapshot
Undoped SiGe material calibration for numerical nanosecond laser annealing simulations
inferred← citeshttps://doi.org/10.70675/30476633zcfa0z4d93z9db2zc40bacdb4767openalex-snapshot
Transferring mechanical stress from SiN to Si upon nanosecond laser annealing
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