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An Emerging Local Annealing Method for Simultaneous Crystallization and Activation in Three-Dimensional Nand Flash
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inferredcites →https://doi.org/10.1016/j.sse.2013.01.023openalex-extracted
Analysis of USJ formation with combined RTA/laser annealing conditions for 28nm high-k/metal gate CMOS technology using advanced TCAD for process and device simulation
inferredcites →https://doi.org/10.1109/essderc.2009.5331536openalex-extracted
Managing annealing pattern effects in 45nm low power CMOS technology
inferredcites →https://doi.org/10.1109/iedm.2008.4796763openalex-extracted
3D stacked IC demonstration using a through Silicon Via First approach
inferredcites →https://doi.org/10.1109/iedm.2013.6724555openalex-extracted
A novel dual-channel 3D NAND flash featuring both N-channel and P-channel NAND characteristics for bit-alterable Flash memory and a new opportunity in sensing the stored charge in the WL space
inferredcites →https://doi.org/10.1109/iedm.2018.8614708openalex-extracted
Location-controlled-grain Technique for Monolithic 3D BEOL FinFET Circuits
inferredcites →https://doi.org/10.1109/iedm19574.2021.9720614openalex-extracted
3D SoC integration, beyond 2.5D chiplets
inferredcites →https://doi.org/10.1109/iirw.2017.8361235openalex-extracted
2D vs 3D NAND technology: Reliability benchmark
inferredcites →https://doi.org/10.1109/iit.2014.6940000openalex-extracted
Dopant profile engineering using ArF excimer laser, flash lamp and spike annealing for junction formation
inferredcites →https://doi.org/10.1109/irps46558.2021.9405115openalex-extracted
Excellent Reliability of Xtacking™ Bonding Interface
inferredcites →https://doi.org/10.1109/ispsd.2006.1666063openalex-extracted
A New Isolation Technique for Reverse Blocking IGBT with Ion Implantation and Laser Annealing to Tapered Chip Edge Sidewalls
inferredcites →https://doi.org/10.1109/iwjt.2010.5474997openalex-extracted
Millisecond anneal for ultra-shallow junction applications
inferredcites →https://doi.org/10.1109/jeds.2014.2339296openalex-extracted
Via Diode in Cu Backend Process for 3D Cross-Point RRAM Arrays
inferredcites →https://doi.org/10.1109/jeds.2018.2804383openalex-extracted
FinFET Versus Gate-All-Around Nanowire FET: Performance, Scaling, and Variability
inferredcites →https://doi.org/10.1109/jssc.2020.3036341openalex-extracted
IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management
inferredcites →https://doi.org/10.1109/led.2008.2001029openalex-extracted
Laser Annealing of Amorphous Germanium on Silicon–Germanium Source/Drain for Strain and Performance Enhancement in pMOSFETs
inferredcites →https://doi.org/10.1109/led.2018.2875751openalex-extracted
Low-Temperature Hybrid Dopant Activation Technique Using Pulsed Green Laser for Heavily-Doped n-Type SiGe Source/Drain
inferredcites →https://doi.org/10.1109/led.2018.2883770openalex-extracted
Investigation of Erase Cycling Induced TSG Vt Shift in 3D NAND Flash Memory
inferredcites →https://doi.org/10.1109/tgrs.2020.3010305openalex-extracted
Recurrent Neural Network for Rain Estimation Using Commercial Microwave Links
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