On the public citation graph

Automatic decomposition for sequential equivalence checking of system level and RTL descriptions

https://doi.org/10.1109/memcod.2006.1695903
0 signed · 39 inferred · view as graph

Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

Is this your work? Sign in with ORCID and put your name on the claims that are yours.
Claim with ORCID
Reference health. See whether every reference in this work resolves to a known work and none has been retracted — and get a dated CiteStamped badge you can embed.
See reference health

What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/s10009-004-0183-4openalex-snapshot
A survey of recent advances in SAT-based formal verification
inferredcites →https://doi.org/10.1093/ietfec/e88-a.12.3315openalex-snapshot
An Equivalence Checking Method for C Descriptions Based on Symbolic Simulation with Textual Differences
inferredcites →https://doi.org/10.1109/dac.2002.1012640openalex-snapshot
A practical and efficient method for compare-point matching
inferredcites →https://doi.org/10.1109/date.2005.55openalex-snapshot
An Efficient Sequential SAT Solver With Improved Search Strategies
inferredcites →https://doi.org/10.1109/mdt.2001.936243openalex-snapshot
Formal verification of commercial integrated circuits
inferredcites →https://doi.org/10.1109/tc.2007.1073openalex-snapshot
Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems
inferredcites →https://doi.org/10.1109/test.2002.1041761openalex-snapshot
Verifying properties using sequential ATPG [IC design]
inferredcites →https://doi.org/10.1109/tit.1967.1054010openalex-snapshot
Error bounds for convolutional codes and an asymptotically optimum decoding algorithm
inferredcites →https://doi.org/10.1145/1119772.1119831openalex-snapshot
Hardware verification using ANSI-C programs as a reference
inferredcites →https://doi.org/10.1145/288548.289087openalex-snapshot
Robust latch mapping for combinational equivalence checking
inferredcites →https://doi.org/10.1145/375977.376022openalex-snapshot
Verifying sequential equivalence using ATPG techniques
inferredcites →https://doi.org/10.1145/513918.513951openalex-snapshot
RTL c-based methodology for designing and verifying a multi-threaded processor
inferredcites →https://doi.org/10.1145/513918.513997openalex-snapshot
A practical and efficient method for compare-point matching
inferredcites →https://doi.org/10.1145/775832.775928openalex-snapshot
Behavioral consistency of C and verilog programs using bounded model checking
inferredcites →https://doi.org/10.21236/ada461052openalex-snapshot
Behavioral Consistency of C and Verilog Programs Using Bounded Model Checking

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-540-75596-8_11openalex-snapshot
Automatic Merge-Point Detection for Sequential Equivalence Checking of System-Level and RTL Descriptions
inferred← citeshttps://doi.org/10.1007/978-3-540-89985-3_85openalex-snapshot
Sequential Equivalence Checking Using a Hybrid Boolean-Word Level Decision Diagram
inferred← citeshttps://doi.org/10.1007/978-3-642-39611-3_24openalex-snapshot
FoREnSiC– An Automatic Debugging Environment for C Programs
inferred← citeshttps://doi.org/10.1007/s10617-008-9033-zopenalex-snapshot
Sequential equivalence checking between system level and RTL descriptions
inferred← citeshttps://doi.org/10.1007/s10836-015-5528-2openalex-snapshot
A Unified Sequential Equivalence Checking Methodology to Verify RTL Designs with High-Level Functional and Protocol Specification Models
inferred← citeshttps://doi.org/10.1007/s11704-015-4257-0openalex-snapshot
Equivalence checking between SLM and TLM using coverage directed simulation
inferred← citeshttps://doi.org/10.1016/j.micpro.2013.10.002openalex-snapshot
Formal equivalence verification and debugging techniques with auto-correction mechanism for RTL designs
inferred← citeshttps://doi.org/10.1109/cadgraphics.2013.21openalex-snapshot
Equivalence Checking between SLM and TLM Using Coverage Directed Simulation
inferred← citeshttps://doi.org/10.1109/ddecs.2013.6549789openalex-snapshot
Debugging HDL designs based on functional equivalences with high-level specifications
inferred← citeshttps://doi.org/10.1109/ddecs.2017.7934569openalex-snapshot
Mapping abstract and concrete hardware models for design understanding
inferred← citeshttps://doi.org/10.1109/ewdts.2008.5580149openalex-snapshot
RTL-TLM equivalence checking based on simulation
inferred← citeshttps://doi.org/10.1109/hldvt.2009.5340179openalex-snapshot
STAR: Generating input vectors for design validation by static analysis of RTL
inferred← citeshttps://doi.org/10.1109/iccd.2017.37openalex-snapshot
Automated Debugging of Arithmetic Circuits Using Incremental Gröbner Basis Reduction
inferred← citeshttps://doi.org/10.1109/isqed.2008.4479812openalex-snapshot
2D Decomposition Sequential Equivalence Checking of System Level and RTL Descriptions
inferred← citeshttps://doi.org/10.1109/memcod.2007.371236openalex-snapshot
Towards Equivalence Checking Between TLM and RTL Models
inferred← citeshttps://doi.org/10.1109/tc.2009.78openalex-snapshot
An Automated Framework for Accelerating Numerical Algorithms on Reconfigurable Platforms Using Algorithmic/Architectural Optimization
inferred← citeshttps://doi.org/10.1109/tc.2010.187openalex-snapshot
Automatic Abstraction of RTL IPs into Equivalent TLM Descriptions
inferred← citeshttps://doi.org/10.1109/vlsi.design.2009.85openalex-snapshot
Dedicated Rewriting: Automatic Verification of Low Power Transformations in RTL
inferred← citeshttps://doi.org/10.1109/vlsid.2013.208openalex-snapshot
Assertion-Based Functional Consistency Checking between TLM and RTL Models
inferred← citeshttps://doi.org/10.1142/s0218126621500742openalex-snapshot
A Path-Based Equivalence Checking Method Between System Level and RTL Descriptions Using Machine Learning
inferred← citeshttps://doi.org/10.1145/1973009.1973054openalex-snapshot
Simulation-based equivalence checking between SystemC models at different levels of abstraction
inferred← citeshttps://doi.org/10.1145/2463209.2488808openalex-snapshot
VeriTrust
inferred← citeshttps://doi.org/10.1145/2463209.2488878openalex-snapshot
Handling design and implementation optimizations in equivalence checking for behavioral synthesis
inferred← citeshttps://doi.org/10.15760/etd.2459openalex-snapshot
Scalable Equivalence Checking for Behavioral Synthesis
Editorial review for independent work. ICSAC — the Institute for Complexity Science and Advanced Computing — runs a structured editorial panel for researchers publishing outside journals, and publishes on CiteStamp rails. Submission is free and goes through ORCID: icsacinstitute.org/submit.