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An Efficient Sequential SAT Solver With Improved Search Strategies
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-45657-0_19openalex-snapshot
Applying SAT Methods in Unbounded Symbolic Model Checking
inferredcites →https://doi.org/10.1007/3-540-45657-0_29openalex-snapshot
NuSMV 2: An OpenSource Tool for Symbolic Model Checking
inferredcites →https://doi.org/10.1007/3-540-63104-6_28openalex-snapshot
SATO: An efficient propositional prover
inferredcites →https://doi.org/10.1016/0377-2217(90)90290-ropenalex-snapshot
Digital Systems : Testing and Testable Design
inferredcites →https://doi.org/10.1109/12.769433openalex-snapshot
GRASP: a search algorithm for propositional satisfiability
inferredcites →https://doi.org/10.1109/43.856977openalex-snapshot
IGRAINE-an Implication GRaph-bAsed engINE for fast implication, justification, and propagation
inferredcites →https://doi.org/10.1109/9780470544389openalex-snapshot
Digital Systems Testing and Testable Design
inferredcites →https://doi.org/10.1109/dac.1999.781333openalex-snapshot
Symbolic model checking using SAT procedures instead of BDDs
inferredcites →https://doi.org/10.1109/dac.2002.1012722openalex-snapshot
Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver
inferredcites →https://doi.org/10.1109/date.2002.998262openalex-snapshot
BerkMin: A fast and robust SAT-solver
inferredcites →https://doi.org/10.1109/date.2004.1268860openalex-snapshot
A novel SAT all-solutions solver for efficient preimage computation
inferredcites →https://doi.org/10.1109/iccad.1997.643607openalex-snapshot
A SAT-based implication engine for efficient ATPG, equivalence checking, and optimization of netlists
inferredcites →https://doi.org/10.1109/iccad.2001.968634openalex-snapshot
Efficient conflict driven learning in a Boolean satisfiability solver
inferredcites →https://doi.org/10.1109/iccad.2003.159706openalex-snapshot
SATORI-a fast sequential SAT engine for circuits
inferredcites →https://doi.org/10.1145/309847.309942openalex-snapshot
Symbolic model checking using SAT procedures instead of BDDs
inferredcites →https://doi.org/10.1145/513918.514105openalex-snapshot
Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver
inferredcites →https://doi.org/10.1145/775832.776043openalex-snapshot
SAT-based unbounded symbolic model checking
inferredcites →https://doi.org/10.5555/1015090.1015195openalex-snapshot
Efficient reachability checking using sequential SAT
inferredcites →https://doi.org/10.5555/266388.266569openalex-snapshot
A SAT-based implication engine for efficient ATPG, equivalence checking, and optimization of netlists
inferredcites →https://doi.org/10.5555/789083.1022837openalex-snapshot
A Circuit SAT Solver With Signal Correlation Guided Learning
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-319-48989-6_28openalex-snapshot
Towards Concolic Testing for Hybrid Systems
inferred← citeshttps://doi.org/10.1007/978-3-642-01748-3_15openalex-snapshot
Hybrid BDD and All-SAT Method for Model Checking
inferred← citeshttps://doi.org/10.1007/s10617-008-9033-zopenalex-snapshot
Sequential equivalence checking between system level and RTL descriptions
inferred← citeshttps://doi.org/10.1093/logcom/exn041openalex-snapshot
From (Quantified) Boolean Formulae to Answer Set Programming
inferred← citeshttps://doi.org/10.1109/aspdac.2006.1594640openalex-snapshot
Generation of shorter sequences for high resolution error diagnosis using sequential SAT
inferred← citeshttps://doi.org/10.1109/ats.2007.80openalex-snapshot
An Efficient Diagnostic Test Pattern Generation Framework Using Boolean Satisfiability
inferred← citeshttps://doi.org/10.1109/dac18074.2021.9586331openalex-snapshot
Deep Integration of Circuit Simulator and SAT Solver
inferred← citeshttps://doi.org/10.1109/famcad.2007.12openalex-snapshot
Automated Extraction of Inductive Invariants to Aid Model Checking
inferred← citeshttps://doi.org/10.1109/fmcad.2007.9openalex-snapshot
Automated Extraction of Inductive Invariants to Aid Model Checking
inferred← citeshttps://doi.org/10.1109/hldvt.2005.1568812openalex-snapshot
Sequential equivalence checking based on k-th invariants and circuit SAT solving
inferred← citeshttps://doi.org/10.1109/icasic.2007.4415843openalex-snapshot
An efficient sequential equivalence checking framework using Boolean Satisfiability
inferred← citeshttps://doi.org/10.1109/iccad.2007.4397272openalex-snapshot
A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test
inferred← citeshttps://doi.org/10.1109/iccad51958.2021.9643505openalex-snapshot
A Circuit-Based SAT Solver for Logic Synthesis
inferred← citeshttps://doi.org/10.1109/iccd.2005.18openalex-snapshot
Accurate diagnosis of multiple faults
inferred← citeshttps://doi.org/10.1109/iccd.2005.99openalex-snapshot
State set management for SAT-based unbounded model checking
inferred← citeshttps://doi.org/10.1109/iita.2008.322openalex-snapshot
Formal Verification of Controller Synthesis Based on Incompletely Specified Finite State Machine Model
inferred← citeshttps://doi.org/10.1109/isise.2008.274openalex-snapshot
Verification of Controller Synthesis Based on Completely Specified Finite State Machine
inferred← citeshttps://doi.org/10.1109/memcod.2006.1695903openalex-snapshot
Automatic decomposition for sequential equivalence checking of system level and RTL descriptions
inferred← citeshttps://doi.org/10.1109/mtv.2005.14openalex-snapshot
Language-driven Validation of Pipelined Processors using Satisfiability Solvers
inferred← citeshttps://doi.org/10.1109/tcad.2006.882511openalex-snapshot
Simulation-Based Bug Trace Minimization With BMC-Based Refinement
inferred← citeshttps://doi.org/10.1109/tcad.2006.884486openalex-snapshot
Multiple-Fault Diagnosis Based On Adaptive Diagnostic Test Pattern Generation
inferred← citeshttps://doi.org/10.1109/test.2006.297644openalex-snapshot
A Unified Approach to Test Generation and Test Data Volume Reduction
inferred← citeshttps://doi.org/10.1109/test.2008.4700566openalex-snapshot
CONCAT: CONflict Driven Learning in ATPG for Industrial designs
inferred← citeshttps://doi.org/10.1109/test.2008.4700568openalex-snapshot
RTL Error Diagnosis Using a Word-Level SAT-Solver
inferred← citeshttps://doi.org/10.1109/tvlsi.2008.2005311openalex-snapshot
SEChecker: A Sequential Equivalence Checking Framework Based on ${K}$th Invariants
inferred← citeshttps://doi.org/10.1109/vlsid.2007.80openalex-snapshot
Explicit Safety Property Strengthening in SAT-based Induction
inferred← citeshttps://doi.org/10.1109/vts.2005.69openalex-snapshot
Pseudo-Functional Scan-based BIST for Delay Fault
inferred← citeshttps://doi.org/10.1109/vts.2011.5783736openalex-snapshot
Low Coverage Analysis using dynamic un-testability debug in ATPG
inferred← citeshttps://doi.org/10.1145/3511094openalex-snapshot
Energy Efficient Computing Systems: Architectures, Abstractions and Modeling to Techniques and Standards
inferred← citeshttps://doi.org/10.4028/www.scientific.net/amr.204-210.251openalex-snapshot
Sequential Circuit Equivalence Checking Method Based on Minimizing Automation
inferred← citeshttps://doi.org/10.5555/1129601.1129748openalex-snapshot
Simulation-based bug trace minimization with BMC-based refinement
inferred← citeshttps://doi.org/10.5555/1326073.1326122openalex-snapshot
A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test
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