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Design, Implementation, and Validation of a New Class of Interface Circuits for Latency-Insensitive Design
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-48683-6_44openalex-snapshot
NuSMV: A New Symbolic Model Verifier
inferredcites →https://doi.org/10.1016/0012-365x(78)90011-0openalex-snapshot
A characterization of the minimum cycle mean in a digraph
inferredcites →https://doi.org/10.1016/j.entcs.2005.05.036openalex-snapshot
The Role of Back-Pressure in Implementing Latency-Insensitive Systems
inferredcites →https://doi.org/10.1109/2.612245openalex-snapshot
Will physical scalability sabotage performance gains?
inferredcites →https://doi.org/10.1109/43.728912openalex-snapshot
Faster maximum and minimum mean cycle algorithms for system-performance analysis
inferredcites →https://doi.org/10.1109/43.736561openalex-snapshot
A framework for comparing models of computation
inferredcites →https://doi.org/10.1109/43.945302openalex-snapshot
Theory of latency-insensitive design
inferredcites →https://doi.org/10.1109/async.2002.1000291openalex-snapshot
Synchronous interlocked pipelines
inferredcites →https://doi.org/10.1109/date.2004.1269025openalex-snapshot
Generalized latency-insensitive systems for single-clock and multi-clock architectures
inferredcites →https://doi.org/10.1109/iccad.1999.810667openalex-snapshot
A methodology for correct-by-construction latency insensitive design
inferredcites →https://doi.org/10.1109/iccad.2005.1560209openalex-snapshot
An architecture and a wrapper synthesis approach for multi-clock latency-insensitive systems
inferredcites →https://doi.org/10.1109/jproc.2002.805826openalex-snapshot
The synchronous languages 12 years later
inferredcites →https://doi.org/10.1109/mm.2002.1044297openalex-snapshot
Coping with latency in SOC design
inferredcites →https://doi.org/10.1109/tc.2006.188openalex-snapshot
Validating Families of Latency Insensitive Protocols
inferredcites →https://doi.org/10.1109/tcad.2005.854636openalex-snapshot
Performance analysis of latency-insensitive systems
inferredcites →https://doi.org/10.1109/tse.1980.230492openalex-snapshot
Performance Evaluation of Asynchronous Concurrent Systems Using Petri Nets
inferredcites →https://doi.org/10.1109/tvlsi.2004.831476openalex-snapshot
Robust interfaces for mixed-timing systems
inferredcites →https://doi.org/10.1145/1146909.1147077openalex-snapshot
Synthesis of synchronous elastic architectures
inferredcites →https://doi.org/10.1145/1278480.1278586openalex-snapshot
Topology-based optimization of maximal sustainable throughput in a latency-insensitive system
inferredcites →https://doi.org/10.1145/337292.337441openalex-snapshot
Performance analysis and optimization of latency insensitive systems
inferredcites →https://doi.org/10.1145/996566.996725openalex-snapshot
A new approach to latency insensitive design
inferredcites →https://doi.org/10.5555/1129601.1129743openalex-snapshot
An architecture and a wrapper synthesis approach for multi-clock latency-insensitive systems
inferredcites →https://doi.org/10.5555/968879.969143openalex-snapshot
Generalized latency-insensitive systems for single-clock and multi-clock architectures
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1016/j.entcs.2009.07.025openalex-snapshot
Modeling and Analyzing the Implementation of Latency-Insensitive Protocols Using the Polychrony Framework
inferred← citeshttps://doi.org/10.1016/j.vlsi.2012.06.001openalex-snapshot
A formal framework for interfacing mixed-timing systems
inferred← citeshttps://doi.org/10.1049/iet-cdt.2010.0023openalex-snapshot
Refinement-based verification of elastic pipelined systems
inferred← citeshttps://doi.org/10.1049/iet-cdt.2010.0116openalex-snapshot
Half-buffer retiming and token cages for synchronous elastic circuits
inferred← citeshttps://doi.org/10.1049/iet-cdt.2013.0121openalex-snapshot
Heuristic algorithm for periodic clock optimisation in scheduling‐based latency‐insensitive design
inferred← citeshttps://doi.org/10.1109/async.2010.16openalex-snapshot
Improving Synchronous Elastic Circuits: Token Cages and Half-Buffer Retiming
inferred← citeshttps://doi.org/10.1109/date.2010.5457005openalex-snapshot
Exploiting local logic structures to optimize multi-core SoC floorplanning
inferred← citeshttps://doi.org/10.1109/iccad.2007.4397240openalex-snapshot
Using functional independence conditions to optimize the performance of latency-insensitive systems
inferred← citeshttps://doi.org/10.1109/icrc64395.2024.10937010openalex-snapshot
Superconnectors: A Latency Insensitive Approach to SFQ Design
inferred← citeshttps://doi.org/10.1109/jproc.2015.2480849openalex-snapshot
From Latency-Insensitive Design to Communication-Based System-Level Design
inferred← citeshttps://doi.org/10.1109/memcod.2010.5558635openalex-snapshot
Minimizing back pressure for latency insensitive system synthesis
inferred← citeshttps://doi.org/10.1109/memcod.2015.7340485openalex-snapshot
Implementing latency-insensitive dataflow blocks
inferred← citeshttps://doi.org/10.1109/tc.2008.214openalex-snapshot
A Process Algebraic View of Latency-Insensitive Systems
inferred← citeshttps://doi.org/10.1109/tcad.2008.2008914openalex-snapshot
Topology-Based Performance Analysis and Optimization of Latency-Insensitive Systems
inferred← citeshttps://doi.org/10.1109/tcad.2008.2009157openalex-snapshot
Leveraging Local Intracore Information to Increase Global Performance in Block-Based Design of Systems-on-Chip
inferred← citeshttps://doi.org/10.1109/tvlsi.2008.2000869openalex-snapshot
A Trace-Based Framework for Verifiable GALS Composition of IPs
inferred← citeshttps://doi.org/10.1145/2554688.2554786openalex-snapshot
Quantifying the cost and benefit of latency insensitive communication on FPGAs
inferred← citeshttps://doi.org/10.1145/3127041.3127055openalex-snapshot
Compositional dataflow circuits
inferred← citeshttps://doi.org/10.1145/3534971openalex-snapshot
High-level Modeling and Verification Platform for Elastic Circuits with Process Variation Considerations
inferred← citeshttps://doi.org/10.48550/arxiv.2102.06326openalex-snapshot
Verifying High-Level Latency-Insensitive Designs with Formal Model Checking
inferred← citeshttps://doi.org/10.7916/d8-4yxc-gz97openalex-snapshot
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