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Compositional Dataflow Circuits

https://doi.org/10.1145/3274280
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-1-4614-4301-8openalex-snapshot
Microarchitecture of Network-on-Chip Routers: A Designer's Perspective
inferredcites →https://doi.org/10.1007/s11265-009-0397-5openalex-snapshot
Synthesizing Hardware from Dataflow Programs
inferredcites →https://doi.org/10.1016/0026-2714(86)90023-5openalex-snapshot
Introduction to VLSI systems
inferredcites →https://doi.org/10.1016/0167-6423(88)90016-0openalex-snapshot
Nondeterministic data flow programs: How to avoid the merge anomaly
inferredcites →https://doi.org/10.1016/j.entcs.2005.05.036openalex-snapshot
The Role of Back-Pressure in Implementing Latency-Insensitive Systems
inferredcites →https://doi.org/10.1108/ir.1999.04926fae.001openalex-snapshot
Lecture Notes in Computer Science 1205
inferredcites →https://doi.org/10.1109/43.945302openalex-snapshot
Theory of latency-insensitive design
inferredcites →https://doi.org/10.1109/5.381846openalex-snapshot
Dataflow process networks
inferredcites →https://doi.org/10.1109/fdl33691.2014openalex-snapshot
Proceedings of the 2014 Forum on Specification and Design Languages (FDL)
inferredcites →https://doi.org/10.1109/icassp.1992.226558openalex-snapshot
Well-behaved dataflow programs for DSP computation
inferredcites →https://doi.org/10.1109/iccd.2016.7753285openalex-snapshot
Fluid Pipelines: Elastic circuitry meets Out-of-Order execution
inferredcites →https://doi.org/10.1109/memcod.2007.371256openalex-snapshot
Design, Implementation, and Validation of a New Class of Interface Circuits for Latency-Insensitive Design
inferredcites →https://doi.org/10.1109/memcod.2010.5558639openalex-snapshot
Elastic systems
inferredcites →https://doi.org/10.1109/memcod.2015.7340485openalex-snapshot
Implementing latency-insensitive dataflow blocks
inferredcites →https://doi.org/10.1109/samos.2014.6893194openalex-snapshot
On tokens and signals: Bridging the semantic gap between dataflow models and hardware implementations
inferredcites →https://doi.org/10.1109/tc.2008.58openalex-snapshot
Throughput-Buffering Trade-Off Exploration for Cyclo-Static and Synchronous Dataflow Graphs
inferredcites →https://doi.org/10.1109/tc.2009.155openalex-snapshot
Buffer Sizing for Rate-Optimal Single-Rate Data-Flow Scheduling Revisited
inferredcites →https://doi.org/10.1109/tcad.2009.2030436openalex-snapshot
Elastic Circuits
inferredcites →https://doi.org/10.1145/1065579.1065796openalex-snapshot
Minimising buffer requirements of synchronous dataflow graphs with model checking
inferredcites →https://doi.org/10.1145/1455229.1455230openalex-snapshot
SystemCoDesigner—an automatic ESL synthesis approach by design space exploration and behavioral synthesis for streaming applications
inferredcites →https://doi.org/10.1145/1878961.1878985openalex-snapshot
Worst-case performance analysis of synchronous dataflow scenarios
inferredcites →https://doi.org/10.1145/2638550openalex-snapshot
Energy Analysis of Hardware and Software Range Partitioning
inferredcites →https://doi.org/10.1145/3033019.3033027openalex-snapshot
From functional programs to pipelined dataflow circuits
inferredcites →https://doi.org/10.1145/3318.3480openalex-snapshot
Efficient demand-driven evaluation. Part 1
inferredcites →https://doi.org/10.1145/373243.360209openalex-snapshot
Regular expression pattern matching for XML
inferredcites →https://doi.org/10.1145/581199.581219openalex-snapshot
A case study of hardware and software synthesis in ForSyDe
inferredcites →https://doi.org/10.1145/767193.767195openalex-snapshot
XDuce
inferredcites →https://doi.org/10.1155/2007/47580openalex-snapshot
A SystemC-Based Design Methodology for Digital Signal Processing Systems

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-981-15-6401-7_19-1openalex-snapshot
Accelerator Design with High-Level Synthesis
inferred← citeshttps://doi.org/10.1007/978-981-97-9314-3_19openalex-snapshot
Accelerator Design with High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/fpl57034.2022.00019openalex-snapshot
Synthesized In-BramGarbage Collection for Accelerators with Immutable Memory
inferred← citeshttps://doi.org/10.1109/fpl60245.2023.00009openalex-snapshot
Compiler Discovered Dynamic Scheduling of Irregular Code in High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/icrc64395.2024.10937010openalex-snapshot
Superconnectors: A Latency Insensitive Approach to SFQ Design
inferred← citeshttps://doi.org/10.1145/3469660openalex-snapshot
Programming and Synthesis for Software-defined FPGA Acceleration: Status and Future Prospects
inferred← citeshttps://doi.org/10.1145/3486609.3487198openalex-snapshot
Metaprogramming with combinators
inferred← citeshttps://doi.org/10.1145/3534971openalex-snapshot
High-level Modeling and Verification Platform for Elastic Circuits with Process Variation Considerations
inferred← citeshttps://doi.org/10.1145/3575693.3575701openalex-snapshot
ShakeFlow: Functional Hardware Description with Latency-Insensitive Interface Combinators
inferred← citeshttps://doi.org/10.1145/3705732openalex-snapshot
A Speculative Loop Pipeline Framework with Accurate Path Modeling for High-Level Synthesis
inferred← citeshttps://doi.org/10.1145/3720432openalex-snapshot
A Mechanized Semantics for Dataflow Circuits
inferred← citeshttps://doi.org/10.1145/3742875.3754682openalex-snapshot
Automated Power Domain Insertion and Control in Dataflow Circuits
inferred← citeshttps://doi.org/10.1145/3748173.3779204openalex-snapshot
Out with LSQs: Custom Circuits for Memory Access Reordering in Dynamic HLS
inferred← citeshttps://doi.org/10.1145/3814943.3816183openalex-snapshot
A Functional Approach to Synthesizing Routable Programmable Accelerators for Neural Networks
inferred← citeshttps://doi.org/10.20868/upm.thesis.65388openalex-snapshot
A Framework to Support Run-Time Adaptation in Reconfigurable Multi-Accelerator Systems
inferred← citeshttps://doi.org/10.3390/electronics14234578openalex-snapshot
A Source-to-Source Compiler to Enable Hybrid Scheduling for High-Level Synthesis
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