On the public citation graph

GPU-based NoC simulator

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Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/hpca.2011.5749747openalex-snapshot
HAsim: FPGA-based high-detail multicore simulation using time-division multiplexing
inferredcites →https://doi.org/10.1109/memcod.2011.5970512openalex-snapshot
MEMOCODE 2011 Hardware/Software CoDesign Contest: NoC simulator

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1109/aspdac.2017.7858401openalex-snapshot
Detailed and highly parallelizable cycle-accurate network-on-chip simulation on GPGPU
inferred← citeshttps://doi.org/10.1109/candar.2017.52openalex-snapshot
Large-Scale Interconnection Network Simulation Methods Based on Cellular Automata
inferred← citeshttps://doi.org/10.1109/icecs.2018.8617979openalex-snapshot
Exploring MAS to a High Level Abstration NoC Simulation Environment
inferred← citeshttps://doi.org/10.1109/indicon.2014.7030460openalex-snapshot
DDGSim: GPU based simulator for large multicore with bufferless NoC
inferred← citeshttps://doi.org/10.1109/nocs.2013.6558402openalex-snapshot
Scalable parallel simulation of networks on chip
inferred← citeshttps://doi.org/10.1109/pdp.2016.118openalex-snapshot
Globally Asynchronous Locally Synchronous Simulation of NoCs on Many-Core Architectures
inferred← citeshttps://doi.org/10.1145/2613908.2613918openalex-snapshot
A GALS Router for Asynchronous Network-on-Chip
inferred← citeshttps://doi.org/10.1145/2870633openalex-snapshot
Performance Evaluation of NoC-Based Multicore Systems
inferred← citeshttps://doi.org/10.1587/transinf.2018edp7131openalex-snapshot
Accelerating Large-Scale Interconnection Network Simulation by Cellular Automata Concept
inferred← citeshttps://doi.org/10.23919/cje.2014.10851236openalex-snapshot
Mixed-Level Modeling Methodology for Network-on-Chip Architecture Exploration
inferred← citeshttps://doi.org/10.29292/jics.v16i2.268openalex-snapshot
A Multi-Agent-Based Network-on-Chip Simulator
inferred← citeshttps://doi.org/10.48550/arxiv.1508.03235openalex-snapshot
Bufferless NOC Simulation of Large Multicore System on GPU Hardware
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