On the public citation graph
Performance Evaluation of NoC-Based Multicore Systems
0 signed · 145 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1002/0471200581openalex-snapshot
Queueing Networks and Markov Chains
inferredcites →https://doi.org/10.1002/047120644xopenalex-snapshot
Self‐Similar Network Traffic and Performance Evaluation
inferredcites →https://doi.org/10.1002/0471791571openalex-snapshot
Queueing Networks and Markov Chains
inferredcites →https://doi.org/10.1002/ett.4460120413openalex-snapshot
Performance guarantees in communication networks
inferredcites →https://doi.org/10.1007/11549468_111openalex-snapshot
INSEE: An Interconnection Network Simulation and Evaluation Environment
inferredcites →https://doi.org/10.1007/3-540-46029-2_6openalex-snapshot
Traffic Modeling of IP Networks Using the Batch Markovian Arrival Process
inferredcites →https://doi.org/10.1007/978-1-4020-6488-3_13openalex-snapshot
A Network Traffic Generator Model for Fast Network-on-Chip Simulation
inferredcites →https://doi.org/10.1007/978-1-4471-0459-9openalex-snapshot
Performance Guarantees in Communication Networks
inferredcites →https://doi.org/10.1007/978-1-84800-127-5openalex-snapshot
A Stochastic Network Calculus
inferredcites →https://doi.org/10.1007/978-3-540-30113-4_7openalex-snapshot
Predictable Embedded Multiprocessor System Design
inferredcites →https://doi.org/10.1007/s11227-009-0265-xopenalex-snapshot
Analytical modelling of networks in multicomputer systems under bursty and batch arrival traffic
inferredcites →https://doi.org/10.1007/s11241-010-9108-3openalex-snapshot
Schedulability analysis and task mapping for real-time on-chip communication
inferredcites →https://doi.org/10.1016/0166-5316(93)90035-sopenalex-snapshot
The Markov-modulated Poisson process (MMPP) cookbook
inferredcites →https://doi.org/10.1016/j.media.2009.05.003openalex-snapshot
Fractal and multifractal analysis: A review
inferredcites →https://doi.org/10.1016/s0141-9331(98)00042-8openalex-snapshot
Towards a generic analytical model of wormhole routing networks
inferredcites →https://doi.org/10.1016/s0378-4371(02)01383-3openalex-snapshot
Multifractal detrended fluctuation analysis of nonstationary time series
inferredcites →https://doi.org/10.1016/s0743-7315(02)00055-2openalex-snapshot
Real-time wormhole channels
inferredcites →https://doi.org/10.1016/s1388-3437(97)80058-3openalex-snapshot
An analytical model for wormhole routing with finite size input buffers
inferredcites →https://doi.org/10.1023/a:1016616406118openalex-snapshot
Practical Time-Scale Fitting of Self-Similar Traffic with Markov-Modulated Poisson Process
inferredcites →https://doi.org/10.1023/a:1019165221472openalex-snapshot
On approximating higher order MAPs with MAPs of order two
inferredcites →https://doi.org/10.1023/a:1019199013546openalex-snapshot
MMPP models for multimedia traffic
inferredcites →https://doi.org/10.1080/00401706.1999.10485951openalex-snapshot
Statistical Learning Theory
inferredcites →https://doi.org/10.1108/ir.1999.04926fae.001openalex-snapshot
Lecture Notes in Computer Science 1205
inferredcites →https://doi.org/10.1109/12.817384openalex-snapshot
A performance model for Duato's fully adaptive routing algorithm in k-ary n-cubes
inferredcites →https://doi.org/10.1109/2.976921openalex-snapshot
Networks on chips: a new SoC paradigm
inferredcites →https://doi.org/10.1109/ams.2007.112openalex-snapshot
XMulator: A Listener-Based Integrated Simulation Platform for Interconnection Networks
inferredcites →https://doi.org/10.1109/aspdac.2014.6742910openalex-snapshot
A comprehensive and accurate latency model for Network-on-Chip performance analysis
inferredcites →https://doi.org/10.1109/ccgrid.2011.64openalex-snapshot
GPGPU-Accelerated Parallel and Fast Simulation of Thousand-Core Platforms
inferredcites →https://doi.org/10.1109/date.2004.1268792openalex-snapshot
Proceedings Design, Automation and Test in Europe Conference and Exhibition
inferredcites →https://doi.org/10.1109/date.2005.1openalex-snapshot
×pipes Lite: A Synthesis Oriented Design Library For Networks on Chips
inferredcites →https://doi.org/10.1109/date.2005.22openalex-snapshot
A Network Traffic Generator Model for Fast Network-on-Chip Simulation
inferredcites →https://doi.org/10.1109/date.2005.5openalex-snapshot
A Complete Network-On-Chip Emulation Framework
inferredcites →https://doi.org/10.1109/empdp.2002.994207openalex-snapshot
SICOSYS: an integrated framework for studying interconnection network performance in multiprocessor systems
inferredcites →https://doi.org/10.1109/hpca.2001.903268openalex-snapshot
A delay model and speculative architecture for pipelined routers
inferredcites →https://doi.org/10.1109/hpca.2013.6522340openalex-snapshot
ESESC: A fast multicore simulator using Time-Based Sampling
inferredcites →https://doi.org/10.1109/iccad.2004.1382601openalex-snapshot
Application-specific buffer space allocation for networks-on-chip router design
inferredcites →https://doi.org/10.1109/iccd.1993.393415openalex-snapshot
Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93
inferredcites →https://doi.org/10.1109/iccd.2010.5647577openalex-snapshot
QoS scheduling for NoCs: Strict Priority Queueing versus Weighted Round Robin
inferredcites →https://doi.org/10.1109/icict.2007.375388openalex-snapshot
Gpnocsim - A General Purpose Simulator for Network-On-Chip
inferredcites →https://doi.org/10.1109/iscas.2000.858698openalex-snapshot
Real-time calculus for scheduling hard real-time systems
inferredcites →https://doi.org/10.1109/iscc.2000.860639openalex-snapshot
Fractal traffic models for Internet simulation
inferredcites →https://doi.org/10.1109/ispass.2009.4919636openalex-snapshot
GARNET: A detailed on-chip network model inside a full-system simulator
inferredcites →https://doi.org/10.1109/ispass.2011.5762734openalex-snapshot
Scalable, accurate multicore simulation in the 1000-core era
inferredcites →https://doi.org/10.1109/ispass.2013.6557141openalex-snapshot
Sampled simulation of multi-threaded applications
inferredcites →https://doi.org/10.1109/ispass.2013.6557149openalex-snapshot
A detailed and flexible cycle-accurate Network-on-Chip simulator
inferredcites →https://doi.org/10.1109/isvlsi.2011.49openalex-snapshot
A NoC Traffic Suite Based on Real Applications
inferredcites →https://doi.org/10.1109/isvlsi.2014.36openalex-snapshot
A Case Study on the Communication and Computation Behaviors of Real Applications in NoC-Based MPSoCs
inferredcites →https://doi.org/10.1109/itc2735573.2015openalex-snapshot
2015 27th International Teletraffic Congress
inferredcites →https://doi.org/10.1109/mascots.2006.9openalex-snapshot
A Statistical Traffic Model for On-Chip Interconnection Networks
inferredcites →https://doi.org/10.1109/mcas.2004.1330747openalex-snapshot
Feature - Xpipes : a network-on-chip architecture for gigascale systems-on-chip
inferredcites →https://doi.org/10.1109/mdt.2008.145openalex-snapshot
OCP-IP NoC Benchmarking WG activities
inferredcites →https://doi.org/10.1109/mdt.2012.2205998openalex-snapshot
xMAS: Quick Formal Modeling of Communication Fabrics to Enable Verification
inferredcites →https://doi.org/10.1109/mm.2006.79openalex-snapshot
SimFlex: Statistical Sampling of Computer System Simulation
inferredcites →https://doi.org/10.1109/nocs.2007.18openalex-snapshot
Fast, Accurate and Detailed NoC Simulations
inferredcites →https://doi.org/10.1109/nocs.2007.30openalex-snapshot
NoC Design and Implementation in 65nm Technology
inferredcites →https://doi.org/10.1109/nocs.2007.44openalex-snapshot
Towards Open Network-on-Chip Benchmarks
inferredcites →https://doi.org/10.1109/nocs.2008.4492735openalex-snapshot
Real-Time Communication Analysis for On-Chip Networks with Wormhole Switching
inferredcites →https://doi.org/10.1109/nocs.2008.4492742openalex-snapshot
Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip
inferredcites →https://doi.org/10.1109/nocs.2009.5071444openalex-snapshot
Analysis of worst-case delay bounds for best-effort communication in wormhole networks on chip
inferredcites →https://doi.org/10.1109/nocs.2010.34openalex-snapshot
QuaLe: A Quantum-Leap Inspired Model for Non-stationary Analysis of NoC Traffic in Chip Multi-processors
inferredcites →https://doi.org/10.1109/nocs.2012.19openalex-snapshot
TOPAZ: An Open-Source Interconnection Network Simulator for Chip Multiprocessors and Supercomputers
inferredcites →https://doi.org/10.1109/nocs.2013.6558402openalex-snapshot
Scalable parallel simulation of networks on chip
inferredcites →https://doi.org/10.1109/nocs.2013.6558403openalex-snapshot
An accurate and scalable analytic model for round-robin arbitration in network-on-chip
inferredcites →https://doi.org/10.1109/nocs.2013.6558411openalex-snapshot
Per-flow delay bound analysis based on a formalized microarchitectural model
inferredcites →https://doi.org/10.1109/nocs.2014.7008760openalex-snapshot
Sampling-based approaches to accelerate network-on-chip simulation
inferredcites →https://doi.org/10.1109/nocs.2014.7008761openalex-snapshot
An analytical model for worst-case reorder buffer size of multi-path minimal routing NoCs
inferredcites →https://doi.org/10.1109/nocs.2014.7008762openalex-snapshot
Transient queuing models for input-buffered routers in Network-on-Chip
inferredcites →https://doi.org/10.1109/nocs.2014.7008763openalex-snapshot
Towards stochastic delay bound analysis for Network-on-Chip
inferredcites →https://doi.org/10.1109/pdp.2008.83openalex-snapshot
A Markovian Performance Model for Networks-on-Chip
inferredcites →https://doi.org/10.1109/qest.2008.33openalex-snapshot
KPC-Toolbox: Simple Yet Effective Trace Fitting Using Markovian Arrival Processes
inferredcites →https://doi.org/10.1109/samos.2012.6404157openalex-snapshot
HNOCS: Modular open-source simulator for Heterogeneous NoCs
inferredcites →https://doi.org/10.1109/tc.2004.1275299openalex-snapshot
A performance model for wormhole-switched interconnection networks under self-similar traffic
inferredcites →https://doi.org/10.1109/tc.2011.240openalex-snapshot
Computing Accurate Performance Bounds for Best Effort Networks-on-Chip
inferredcites →https://doi.org/10.1109/tc.2012.85openalex-snapshot
An Iterative Computational Technique for Performance Evaluation of Networks-on-Chip
inferredcites →https://doi.org/10.1109/tcad.2005.844106openalex-snapshot
Energy- and performance-aware mapping for regular NoC architectures
inferredcites →https://doi.org/10.1109/tcad.2010.2043572openalex-snapshot
Analysis of Worst-Case Delay Bounds for On-Chip Packet-Switching Networks
inferredcites →https://doi.org/10.1109/tcad.2010.2061171openalex-snapshot
Power-Performance Analysis of Networks-on-Chip With Arbitrary Buffer Allocation Schemes
inferredcites →https://doi.org/10.1109/tcad.2010.2061613openalex-snapshot
An Analytical Approach for Network-on-Chip Performance Analysis
inferredcites →https://doi.org/10.1109/tcad.2010.2063130openalex-snapshot
Buffer Optimization in Network-on-Chip Through Flow Regulation
inferredcites →https://doi.org/10.1109/tcad.2011.2111270openalex-snapshot
Non-Stationary Traffic Analysis and Its Implications on Multicore Platform Design
inferredcites →https://doi.org/10.1109/tcad.2015.2474393openalex-snapshot
A Support Vector Regression (SVR)-Based Latency Model for Network-on-Chip (NoC) Architectures
inferredcites →https://doi.org/10.1109/tpds.2005.22openalex-snapshot
NoC synthesis flow for customized domain specific multiprocessor systems-on-chip
inferredcites →https://doi.org/10.1109/tvlsi.2003.820523openalex-snapshot
On-chip traffic modeling and synthesis for MPEG-2 video applications
inferredcites →https://doi.org/10.1109/tvlsi.2010.2091686openalex-snapshot
ORION 2.0: A Power-Area Simulator for Interconnection Networks
inferredcites →https://doi.org/10.1109/tvlsi.2011.2178620openalex-snapshot
An Analytical Latency Model for Networks-on-Chip
inferredcites →https://doi.org/10.1145/1119772.1119818openalex-snapshot
Energy-aware mapping for tile-based NoC architectures under performance constraints
inferredcites →https://doi.org/10.1145/1542275.1542341openalex-snapshot
A comprehensive power-performance model for NoCs with multi-flit channel buffers
inferredcites →https://doi.org/10.1145/1629435.1629497openalex-snapshot
Applying network calculus for performance analysis of self-similar traffic in on-chip networks
inferredcites →https://doi.org/10.1145/1629435.1629498openalex-snapshot
Statistical physics approaches for network-on-chip traffic characterization
inferredcites →https://doi.org/10.1145/1629911.1629940openalex-snapshot
Design perspectives on 22nm CMOS and beyond
inferredcites →https://doi.org/10.1145/1687399.1687505openalex-snapshot
An accurate and efficient performance analysis approach based on queuing model for Network on Chip
inferredcites →https://doi.org/10.1145/1687399.1687506openalex-snapshot
A performance analytical model for Network-on-Chip with constant service time routers
inferredcites →https://doi.org/10.1145/1687399.1687507openalex-snapshot
A method for calculating hard QoS guarantees for Networks-on-Chip
inferredcites →https://doi.org/10.1145/1878961.1879003openalex-snapshot
Workload characterization and its impact on multicore platform design
inferredcites →https://doi.org/10.1145/1999946.1999972openalex-snapshot
Delay analysis of wormhole based heterogeneous NoC
inferredcites →https://doi.org/10.1145/2480741.2480755openalex-snapshot
Mathematical formalisms for performance evaluation of networks-on-chip
inferredcites →https://doi.org/10.1145/269790.269792openalex-snapshot
Fast, approximate synthesis of fractional Gaussian noise for generating self-similar network traffic
inferredcites →https://doi.org/10.1145/2786572.2786592openalex-snapshot
Mathematical Modeling and Control of Multifractal Workloads for Data-Center-on-a-Chip Optimization
inferredcites →https://doi.org/10.1145/288548openalex-snapshot
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design - ICCAD '98
inferredcites →https://doi.org/10.1145/321812.321827openalex-snapshot
Application of the Diffusion Approximation to Queueing Networks I: Equilibrium Queue Distributions
inferredcites →https://doi.org/10.1145/513918.514116openalex-snapshot
Traffic analysis for on-chip networks design of multimedia applications
inferredcites →https://doi.org/10.1155/2007/90941openalex-snapshot
Network Delays and Link Capacities in Application-Specific Wormhole NoCs
inferredcites →https://doi.org/10.1201/9780203738481openalex-snapshot
Statistics for Long-Memory Processes
inferredcites →https://doi.org/10.1201/b10477openalex-snapshot
Designing Network On-Chip Architectures in the Nanoscale Era
inferredcites →https://doi.org/10.1561/1000000011openalex-snapshot
The Chip Is the Network: Toward a Science of Network-on-Chip Design
inferredcites →https://doi.org/10.2307/2669582openalex-snapshot
Queueing Networks and Markov Chains: Modeling and Performance Evaluation with Computer Science Applications
inferredcites →https://doi.org/10.2307/2983481openalex-snapshot
Statistics for Long-Memory Processes.
inferredcites →https://doi.org/10.3389/fphys.2012.00141openalex-snapshot
Introduction to Multifractal Detrended Fluctuation Analysis in Matlab
inferredcites →https://doi.org/10.5555/2840819.2840844openalex-snapshot
Mathematical Models and Control Algorithms for Dynamic Optimization of Multicore Platforms: A Complex Dynamics Approach
inferredcites →https://doi.org/10.5555/968878.969037openalex-snapshot
Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-030-43024-5_9openalex-snapshot
On the Stochastic End-to-End Delay Analysis in Sink Trees Under Independent and Dependent Arrivals
inferred← citeshttps://doi.org/10.1007/s11227-019-02971-xopenalex-snapshot
An investigation of latency prediction for NoC-based communication architectures using machine learning techniques
inferred← citeshttps://doi.org/10.1007/s11227-020-03365-0openalex-snapshot
ILP formulation and heuristic method for energy-aware application mapping on 3D-NoCs
inferred← citeshttps://doi.org/10.1016/j.array.2026.100715openalex-snapshot
A novel simulator for performance analysis in heterogeneous wormhole Network-on-Chips
inferred← citeshttps://doi.org/10.1016/j.jpdc.2020.09.013openalex-snapshot
Performance analysis of network-on-chip in many-core processors
inferred← citeshttps://doi.org/10.1016/j.nancom.2017.11.002openalex-snapshot
V-CastNet3D: A novel clustering-based mapping in 3-D Network on chip
inferred← citeshttps://doi.org/10.1016/j.vlsi.2025.102489openalex-snapshot
Semi-adaptive distributed approach for triplet-based architecture inter-core communication Network-on-Chip
inferred← citeshttps://doi.org/10.1049/iet-cdt.2017.0068openalex-snapshot
Comparative analysis of network‐on‐chip simulation tools
inferred← citeshttps://doi.org/10.1109/access.2023.3265572openalex-snapshot
Non-Gaussian Traffic Modeling for Multicore Architecture Using Wavelet Based Rosenblatt Process
inferred← citeshttps://doi.org/10.1109/cimca.2016.8053271openalex-snapshot
Performance analysis: An algorithm for computer performance evaluation using QN model
inferred← citeshttps://doi.org/10.1109/cstic58779.2023.10219215openalex-snapshot
Fast NoC Router Latency Estimation Using Machine Learning
inferred← citeshttps://doi.org/10.1109/eiconrus49466.2020.9039237openalex-snapshot
Analysis of Performance Bottlenecks in SoC Interconnect Subsystems
inferred← citeshttps://doi.org/10.1109/etncc59188.2023.10284966openalex-snapshot
An Artificial Bee Colony Based Mapping Method for Three Dimensional Network-on-Chip
inferred← citeshttps://doi.org/10.1109/igcc.2016.7892616openalex-snapshot
A framework for energy-efficient optimization on multi-cores
inferred← citeshttps://doi.org/10.1109/iscas66217.2026.11562183openalex-snapshot
Slack-Guided Arbitration for Network-on-Chip Congestion Mitigation in Boolean Processor Array Emulation
inferred← citeshttps://doi.org/10.1109/isqed69900.2026.11534721openalex-snapshot
DUA: Detection of Unrecognized Applications Using One-Class SVM in NoC-Based SoCs
inferred← citeshttps://doi.org/10.1109/mdat.2023.3310167openalex-snapshot
Fast Analysis Using Finite Queuing Model for Multilayer NoCs
inferred← citeshttps://doi.org/10.1109/sbac-padw.2016.23openalex-snapshot
An Efficient Channel Model for Evaluating Wireless NoC Architectures
inferred← citeshttps://doi.org/10.1109/tcad.2025.3537971openalex-snapshot
SANA-FE: Simulating Advanced Neuromorphic Architectures for Fast Exploration
inferred← citeshttps://doi.org/10.1109/tcad.2025.3579322openalex-snapshot
Reactive Deadlock Avoidance Based on Focus Routing Graph Classification for Triplet-Based Architecture Network-on-Chip
inferred← citeshttps://doi.org/10.1109/tcsii.2023.3258700openalex-snapshot
Fast and Accurate NoC Latency Estimation for Application-Specific Traffics via Machine Learning
inferred← citeshttps://doi.org/10.1109/wispnet.2017.8300063openalex-snapshot
Performance analysis of 16 × 16, 32 × 32, 64 × 64 2-D mesh topologies for network on chip
inferred← citeshttps://doi.org/10.1155/2018/1040869openalex-snapshot
Hybrid Network‐on‐Chip: An Application‐Aware Framework for Big Data
inferred← citeshttps://doi.org/10.23919/date51398.2021.9474101openalex-snapshot
NoC Performance Model for Efficient Network Latency Estimation
inferred← citeshttps://doi.org/10.29292/jics.v16i2.268openalex-snapshot
A Multi-Agent-Based Network-on-Chip Simulator
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.