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Control Flow Optimization Via Dynamic Reconvergence Prediction

https://doi.org/10.1109/micro.2004.13
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/hpca.1998.650541openalex-snapshot
The potential for using thread-level data speculation to facilitate automatic parallelization
inferredcites →https://doi.org/10.1109/hpca.1999.744346openalex-snapshot
A study of control independence in superscalar processors
inferredcites →https://doi.org/10.1109/hpca.2002.995698openalex-snapshot
Thread-spawning schemes for speculative multithreading
inferredcites →https://doi.org/10.1109/hpca.2004.10028openalex-snapshot
Hardware Support for Prescient Instruction Prefetch
inferredcites →https://doi.org/10.1109/isca.1995.524578openalex-snapshot
Simultaneous multithreading: Maximizing on-chip parallelism
inferredcites →https://doi.org/10.1109/isca.1998.694778openalex-snapshot
Threaded multiple path execution
inferredcites →https://doi.org/10.1109/isca.1998.694785openalex-snapshot
Selective eager execution on the PolyPath architecture
inferredcites →https://doi.org/10.1109/isca.2002.1003587openalex-snapshot
Design tradeoffs for the alpha EV8 conditional branch predictor
inferredcites →https://doi.org/10.1109/isca.2004.1310779openalex-snapshot
Prophet/critic hybrid branch prediction
inferredcites →https://doi.org/10.1109/micro.1998.742784openalex-snapshot
A dynamic multithreading processor
inferredcites →https://doi.org/10.1109/micro.2000.898073openalex-snapshot
Register integration: a simple and efficient implementation of squash reuse
inferredcites →https://doi.org/10.1145/1028176.1006722openalex-snapshot
Prophet/Critic Hybrid Branch Prediction
inferredcites →https://doi.org/10.1145/223982.224449openalex-snapshot
Simultaneous multithreading
inferredcites →https://doi.org/10.1145/223982.224451openalex-snapshot
Multiscalar processors
inferredcites →https://doi.org/10.1145/2591635.2667161openalex-snapshot
The Tera computer system
inferredcites →https://doi.org/10.1145/264107.264200openalex-snapshot
Dynamic instruction reuse
inferredcites →https://doi.org/10.1145/277830.277850openalex-snapshot
Speculative multithreaded processors
inferredcites →https://doi.org/10.1145/279358.279392openalex-snapshot
Threaded multiple path execution
inferredcites →https://doi.org/10.1145/279358.279393openalex-snapshot
Selective eager execution on the PolyPath architecture
inferredcites →https://doi.org/10.1145/305138.305175openalex-snapshot
Reducing branch misprediction penalties via dynamic control independence detection
inferredcites →https://doi.org/10.1145/360128.360151openalex-snapshot
Register integration
inferredcites →https://doi.org/10.1145/545214.545249openalex-snapshot
Design tradeoffs for the Alpha EV8 conditional branch predictor
inferredcites →https://doi.org/10.1145/605397.605403openalex-snapshot
Automatically characterizing large scale program behavior
inferredcites →https://doi.org/10.1145/77726.255132openalex-snapshot
The Tera computer system
inferredcites →https://doi.org/10.1145/781027.781030openalex-snapshot
A framework for modeling and optimization of prescient instruction prefetch
inferredcites →https://doi.org/10.5555/290940.290988openalex-snapshot
A dynamic multithreading processor
inferredcites →https://doi.org/10.5555/320080.320084openalex-snapshot
Control independence in trace processors
inferredcites →https://doi.org/10.5555/563998.564002openalex-snapshot
Skipper: a microarchitecture for exploiting control-flow independence

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-642-00904-4_13openalex-snapshot
Reexecution and Selective Reuse in Checkpoint Processors
inferred← citeshttps://doi.org/10.1007/978-3-642-24650-0_3openalex-snapshot
Dynamic Data Race Detection for Correlated Variables
inferred← citeshttps://doi.org/10.1007/s10766-014-0313-xopenalex-snapshot
Detection of High-Level Synchronization Anomalies in Parallel Programs
inferred← citeshttps://doi.org/10.1016/j.simpat.2018.02.002openalex-snapshot
Simulating heterogeneous behaviours in complex systems on GPUs
inferred← citeshttps://doi.org/10.1109/hpca.2007.346207openalex-snapshot
Exploiting Postdominance for Speculative Parallelization
inferred← citeshttps://doi.org/10.1109/hpca.2008.4658626openalex-snapshot
Performance-aware speculation control using wrong path usefulness prediction
inferred← citeshttps://doi.org/10.1109/hpca.2011.5749713openalex-snapshot
Fg-STP: Fine-Grain Single Thread Partitioning on Multicores
inferred← citeshttps://doi.org/10.1109/hpca.2014.6835939openalex-snapshot
Warp-level divergence in GPUs: Characterization, impact, and mitigation
inferred← citeshttps://doi.org/10.1109/ic-nc.2010.16openalex-snapshot
Control Independence Using Dual Renaming
inferred← citeshttps://doi.org/10.1109/icis.2012.45openalex-snapshot
Distributed Control Independence for Composable Multi-processors
inferred← citeshttps://doi.org/10.1109/igcc.2011.6008593openalex-snapshot
Power and frequency analysis for data and control independence in embedded processors
inferred← citeshttps://doi.org/10.1109/ipdpsw.2014.154openalex-snapshot
Position Paper: Leveraging Strength-Based Dynamic Slicing to Identify Control Reconvergence Instructions
inferred← citeshttps://doi.org/10.1109/isca.2012.6237005openalex-snapshot
Simultaneous branch and warp interweaving for sustained GPU performance
inferred← citeshttps://doi.org/10.1109/isca45697.2020.00019openalex-snapshot
Auto-Predication of Critical Branches
inferred← citeshttps://doi.org/10.1109/isca45697.2020.00020openalex-snapshot
Slipstream Processors Revisited: Exploiting Branch Sets
inferred← citeshttps://doi.org/10.1109/ispass57527.2023.00021openalex-snapshot
Simulating Wrong-Path Instructions in Decoupled Functional-First Simulation
inferred← citeshttps://doi.org/10.1109/micro.2006.20openalex-snapshot
Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths
inferred← citeshttps://doi.org/10.1109/tpds.2009.47openalex-snapshot
Performance Evaluation of Dynamic Speculative Multithreading with the Cascadia Architecture
inferred← citeshttps://doi.org/10.1145/1064978.1065013openalex-snapshot
A serializability violation detector for shared-memory server programs
inferred← citeshttps://doi.org/10.1145/1065010.1065013openalex-snapshot
A serializability violation detector for shared-memory server programs
inferred← citeshttps://doi.org/10.1145/1250662.1250716openalex-snapshot
Ginger
inferred← citeshttps://doi.org/10.1145/1250662.1250717openalex-snapshot
Transparent control independence (TCI)
inferred← citeshttps://doi.org/10.1145/1273440.1250716openalex-snapshot
Ginger
inferred← citeshttps://doi.org/10.1145/1273440.1250717openalex-snapshot
Transparent control independence (TCI)
inferred← citeshttps://doi.org/10.1145/1463768.1463772openalex-snapshot
On the potential of latency tolerant execution in speculative multithreading
inferred← citeshttps://doi.org/10.1145/2086696.2086722openalex-snapshot
SYRANT: SYmmetric resource allocation on not-taken and taken paths
inferred← citeshttps://doi.org/10.1145/2355585.2355592openalex-snapshot
Disjoint out-of-order execution processor
inferred← citeshttps://doi.org/10.1145/2366231.2337166openalex-snapshot
Simultaneous branch and warp interweaving for sustained GPU performance
inferred← citeshttps://doi.org/10.1145/2540708.2540746openalex-snapshot
Trace based phase prediction for tightly-coupled heterogeneous cores
inferred← citeshttps://doi.org/10.1145/3445814.3446726openalex-snapshot
NOREBA: a compiler-informed non-speculative out-of-order commit processor
inferred← citeshttps://doi.org/10.1145/3466752.3480045openalex-snapshot
Enabling Branch-Mispredict Level Parallelism by Selectively Flushing Instructions
inferred← citeshttps://doi.org/10.1145/3466752.3480053openalex-snapshot
Branch Runahead: An Alternative to Branch Prediction for Impossible to Predict Branches
inferred← citeshttps://doi.org/10.1145/3676641.3716028openalex-snapshot
Extended User Interrupts (xUI): Fast and Flexible Notification without Polling
inferred← citeshttps://doi.org/10.1145/3695053.3731059openalex-snapshot
Leveraging control-flow similarity to reduce branch predictor cold effects in microservices
inferred← citeshttps://doi.org/10.1145/3725843.3762248openalex-snapshot
Multi-Stream Squash Reuse for Control-Independent Processors
inferred← citeshttps://doi.org/10.1145/3797155openalex-snapshot
Extended User Interrupts (xUI): Fast and Flexible User-Space Notification for x86 and RISC-V
inferred← citeshttps://doi.org/10.15760/etd.1706openalex-snapshot
Dynamic Task Prediction for an SpMT Architecture Based on Control Independence
inferred← citeshttps://doi.org/10.31390/gradschool_dissertations.1856openalex-snapshot
The weakening of branch predictor performance as an inevitable side effect of exploiting control independence
inferred← citeshttps://doi.org/10.3166/tsi.32.153-178openalex-snapshot
Reconvergence de contrôle implicite pour les architectures SIMT
inferred← citeshttps://doi.org/10.48550/arxiv.2005.14691openalex-snapshot
Dynamic Merge Point Prediction
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