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Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths

https://doi.org/10.1109/micro.2006.20
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/bf03356749openalex-snapshot
Using Predicated Execution to Improve the Performance of a Dynamically Scheduled Machine with Speculative Execution
inferredcites →https://doi.org/10.1109/12.811115openalex-snapshot
Branch prediction, instruction-window size, and cache size: performance trade-offs and simulation techniques
inferredcites →https://doi.org/10.1109/hpca.1997.569617openalex-snapshot
Architectural support for compiler-synthesized dynamic branch prediction strategies: Rationale and initial results
inferredcites →https://doi.org/10.1109/hpca.1999.744346openalex-snapshot
A study of control independence in superscalar processors
inferredcites →https://doi.org/10.1109/hpca.2001.903248openalex-snapshot
Register renaming and scheduling for dynamic execution of predicated code
inferredcites →https://doi.org/10.1109/hpca.2001.903263openalex-snapshot
Dynamic branch prediction with perceptrons
inferredcites →https://doi.org/10.1109/hpca.2003.1183524openalex-snapshot
Incorporating predicate information into branch predictors
inferredcites →https://doi.org/10.1109/hpca.2003.1183532openalex-snapshot
Runahead execution: an alternative to very large instruction windows for out-of-order processors
inferredcites →https://doi.org/10.1109/hpca.2004.10004openalex-snapshot
Reducing Branch Misprediction Penalty via Selective Branch Recovery
inferredcites →https://doi.org/10.1109/isca.1994.288156openalex-snapshot
Guarded execution and branch prediction in dynamic ILP processors
inferredcites →https://doi.org/10.1109/isca.1998.694768openalex-snapshot
Confidence estimation for speculation control
inferredcites →https://doi.org/10.1109/isca.1998.694785openalex-snapshot
Selective eager execution on the PolyPath architecture
inferredcites →https://doi.org/10.1109/isca.2000.854380openalex-snapshot
Wattch: a framework for architectural-level power analysis and optimizations
inferredcites →https://doi.org/10.1109/isca.2002.1003559openalex-snapshot
Increasing processor performance by implementing deeper pipelines
inferredcites →https://doi.org/10.1109/isca.2004.1310761openalex-snapshot
Field-testing IMPACT EPIC research results in itanium 2
inferredcites →https://doi.org/10.1109/isca.2005.13openalex-snapshot
Analysis of the O-GEometric History Length Branch Predictor
inferredcites →https://doi.org/10.1109/l-ca.2002.8openalex-snapshot
MinneSPEC: A New SPEC Benchmark Workload for Simulation-Based Computer Architecture Research
inferredcites →https://doi.org/10.1109/micro.1992.696999openalex-snapshot
Effective Compiler Support For Predicated Execution Using The Hyperblock
inferredcites →https://doi.org/10.1109/micro.1994.717461openalex-snapshot
Characterizing the impact of predicated execution on branch prediction
inferredcites →https://doi.org/10.1109/micro.1996.566457openalex-snapshot
Assigning confidence to conditional branch predictions
inferredcites →https://doi.org/10.1109/micro.1997.645801openalex-snapshot
A framework for balancing control flow and predication
inferredcites →https://doi.org/10.1109/micro.1999.809438openalex-snapshot
Control independence in trace processors
inferredcites →https://doi.org/10.1109/micro.1999.809441openalex-snapshot
Instruction fetch mechanisms for multipath execution processors
inferredcites →https://doi.org/10.1109/micro.2004.13openalex-snapshot
Control Flow Optimization Via Dynamic Reconvergence Prediction
inferredcites →https://doi.org/10.1109/micro.2005.38openalex-snapshot
Wish Branches: Combining Conditional Branching and Predication for Adaptive Predicated Execution
inferredcites →https://doi.org/10.1109/micro.2006.20openalex-snapshot
Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths
inferredcites →https://doi.org/10.1109/mm.2005.49openalex-snapshot
High-Performance Throughput Computing
inferredcites →https://doi.org/10.1109/mm.2005.53openalex-snapshot
Kilo-Instruction Processors: Overcoming the Memory Wall
inferredcites →https://doi.org/10.1109/pact.1998.727261openalex-snapshot
Dynamic hammock predication for non-predicated instruction set architectures
inferredcites →https://doi.org/10.1109/t-c.1972.223514openalex-snapshot
The Inhibition of Potential Parallelism by Conditional Jumps
inferredcites →https://doi.org/10.1145/1024393.1024407openalex-snapshot
Continual flow pipelines
inferredcites →https://doi.org/10.1145/1028176.1006708openalex-snapshot
Microarchitecture Optimizations for Exploiting Memory-Level Parallelism
inferredcites →https://doi.org/10.1145/1028176.1006735openalex-snapshot
Field-testing IMPACT EPIC research results in Itanium 2
inferredcites →https://doi.org/10.1145/1080695.1070003openalex-snapshot
Analysis of the O-GEometric History Length Branch Predictor
inferredcites →https://doi.org/10.1145/115372.115320openalex-snapshot
Efficiently computing static single assignment form and the control dependence graph
inferredcites →https://doi.org/10.1145/139669.139702openalex-snapshot
Limits of control flow on parallelism
inferredcites →https://doi.org/10.1145/144965.144998openalex-snapshot
Effective compiler support for predicated execution using the hyperblock
inferredcites →https://doi.org/10.1145/155090.155118openalex-snapshot
Reverse If-Conversion
inferredcites →https://doi.org/10.1145/191995.192022openalex-snapshot
Guarded execution and branch prediction in dynamic ILP processors
inferredcites →https://doi.org/10.1145/192724.192753openalex-snapshot
The effects of predicated execution on branch prediction
inferredcites →https://doi.org/10.1145/192724.192755openalex-snapshot
Characterizing the impact of predicated execution on branch prediction
inferredcites →https://doi.org/10.1145/277830.277854openalex-snapshot
Multipath execution
inferredcites →https://doi.org/10.1145/279358.279376openalex-snapshot
Confidence estimation for speculation control
inferredcites →https://doi.org/10.1145/279358.279393openalex-snapshot
Selective eager execution on the PolyPath architecture
inferredcites →https://doi.org/10.1145/305138.305175openalex-snapshot
Reducing branch misprediction penalties via dynamic control independence detection
inferredcites →https://doi.org/10.1145/339647.339657openalex-snapshot
Wattch
inferredcites →https://doi.org/10.1145/545214.545219openalex-snapshot
Increasing processor performance by implementing deeper pipelines
inferredcites →https://doi.org/10.1145/567067.567085openalex-snapshot
Conversion of control dependence to data dependence
inferredcites →https://doi.org/10.1147/rd.461.0005openalex-snapshot
POWER4 system microarchitecture
inferredcites →https://doi.org/10.5555/224659.224698openalex-snapshot
Using predicated execution to improve the performance of a dynamically scheduled machine with speculative execution
inferredcites →https://doi.org/10.5555/243846.243880openalex-snapshot
Assigning confidence to conditional branch predictions
inferredcites →https://doi.org/10.5555/266800.266810openalex-snapshot
A framework for balancing control flow and predication
inferredcites →https://doi.org/10.5555/320080.320084openalex-snapshot
Control independence in trace processors
inferredcites →https://doi.org/10.5555/320080.320087openalex-snapshot
Instruction fetch mechanisms for multipath execution processors
inferredcites →https://doi.org/10.5555/522344.825698openalex-snapshot
Dynamic hammock predication for non-predicated instruction set architectures
inferredcites →https://doi.org/10.5555/563998.564002openalex-snapshot
Skipper: a microarchitecture for exploiting control-flow independence
inferredcites →https://doi.org/10.5555/563998.564023openalex-snapshot
The impact of If-conversion and branch prediction on program execution on the Intel/sup R/ Itanium/sup TM/ processor

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1002/cpe.2846openalex-snapshot
A profiling based task scheduling approach for multicore network processors
inferred← citeshttps://doi.org/10.1109/ahs.2010.5546268openalex-snapshot
An emerging adaptive architecture and compilation techniques
inferred← citeshttps://doi.org/10.1109/ahs.2011.5963931openalex-snapshot
A post-manufacturing language-adaptive embedded processor system
inferred← citeshttps://doi.org/10.1109/cgo.2007.31openalex-snapshot
Profile-assisted Compiler Support for Dynamic Predication in Diverge-Merge Processors
inferred← citeshttps://doi.org/10.1109/compsac.2018.10271openalex-snapshot
A Projection-Based Approach for Memory Leak Detection
inferred← citeshttps://doi.org/10.1109/hpca.2008.4658627openalex-snapshot
PaCo: Probability-based path confidence prediction
inferred← citeshttps://doi.org/10.1109/hpca.2008.4658628openalex-snapshot
Branch-mispredict level parallelism (BLP) for control independence
inferred← citeshttps://doi.org/10.1109/hpca.2010.5416632openalex-snapshot
Handling branches in TLS systems with Multi-Path Execution
inferred← citeshttps://doi.org/10.1109/indcon.2013.6725875openalex-snapshot
Security paradigm of FPGA against Differential Power Analysis attack
inferred← citeshttps://doi.org/10.1109/isca45697.2020.00019openalex-snapshot
Auto-Predication of Critical Branches
inferred← citeshttps://doi.org/10.1109/isca59077.2024.00091openalex-snapshot
Alternate Path Fetch
inferred← citeshttps://doi.org/10.1109/isca66397.2026.00052openalex-snapshot
Augmenting the Branch Predictor with a Squashed-Branch Reuse Buffer
inferred← citeshttps://doi.org/10.1109/l-ca.2007.7openalex-snapshot
Dynamic Predication of Indirect Jumps
inferred← citeshttps://doi.org/10.1109/l-ca.2008.2openalex-snapshot
Dynamic Predication of Indirect Jumps
inferred← citeshttps://doi.org/10.1109/micro.2012.38openalex-snapshot
Control-Flow Decoupling
inferred← citeshttps://doi.org/10.1109/mm.2007.9openalex-snapshot
Diverge-Merge Processor: Generalized and Energy-Efficient Dynamic Predication
inferred← citeshttps://doi.org/10.1109/tc.2008.227openalex-snapshot
Virtual Program Counter (VPC) Prediction: Very Low Cost Indirect Branch Prediction Using Conditional Branch Prediction Hardware
inferred← citeshttps://doi.org/10.1109/tc.2014.2361526openalex-snapshot
Control-Flow Decoupling: An Approach for Timely, Non-Speculative Branching
inferred← citeshttps://doi.org/10.1145/1250662.1250715openalex-snapshot
VPC prediction
inferred← citeshttps://doi.org/10.1145/1250662.1250716openalex-snapshot
Ginger
inferred← citeshttps://doi.org/10.1145/1250662.1250717openalex-snapshot
Transparent control independence (TCI)
inferred← citeshttps://doi.org/10.1145/1273440.1250716openalex-snapshot
Ginger
inferred← citeshttps://doi.org/10.1145/1346281.1346293openalex-snapshot
Improving the performance of object-oriented languages with dynamic predication of indirect jumps
inferred← citeshttps://doi.org/10.1145/1353534.1346293openalex-snapshot
Improving the performance of object-oriented languages with dynamic predication of indirect jumps
inferred← citeshttps://doi.org/10.1145/1353535.1346293openalex-snapshot
Improving the performance of object-oriented languages with dynamic predication of indirect jumps
inferred← citeshttps://doi.org/10.1145/1353536.1346293openalex-snapshot
Improving the performance of object-oriented languages with dynamic predication of indirect jumps
inferred← citeshttps://doi.org/10.1145/2355585.2355591openalex-snapshot
Mixed speculative multithreaded execution models
inferred← citeshttps://doi.org/10.1145/2677037openalex-snapshot
Efficient Out-of-Order Execution of Guarded ISAs
inferred← citeshttps://doi.org/10.1145/3466752.3480045openalex-snapshot
Enabling Branch-Mispredict Level Parallelism by Selectively Flushing Instructions
inferred← citeshttps://doi.org/10.48550/arxiv.1707.04657openalex-snapshot
Variable Instruction Fetch Rate to Reduce Control Dependent Penalties
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