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Dynamic Strands: Collapsing Speculative Dependence Chains for Reducing Pipeline Communication
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/12.272427openalex-snapshot
High-performance 3-1 interlock collapsing ALU's
inferredcites →https://doi.org/10.1109/12.931895openalex-snapshot
rePLay: A hardware framework for dynamic optimization
inferredcites →https://doi.org/10.1109/2.917541openalex-snapshot
Instruction-level distributed processing
inferredcites →https://doi.org/10.1109/hpca.1999.744347openalex-snapshot
Instruction pre-processing in trace processors
inferredcites →https://doi.org/10.1109/hpca.2001.903250openalex-snapshot
Speculative data-driven multithreading
inferredcites →https://doi.org/10.1109/isca.1999.765950openalex-snapshot
Simultaneous subordinate microthreading (SSMT)
inferredcites →https://doi.org/10.1109/isca.2002.1003560openalex-snapshot
Efficient dynamic scheduling through tag elimination
inferredcites →https://doi.org/10.1109/jssc.2002.803948openalex-snapshot
A fully bypassed six-issue integer datapath and register file on the Itanium-2 microprocessor
inferredcites →https://doi.org/10.1109/micro.1992.697011openalex-snapshot
Interlock Collapsing ALU For Increased Instruction-level Parallelism
inferredcites →https://doi.org/10.1109/micro.1996.566465openalex-snapshot
The performance potential of data dependence speculation and collapsing
inferredcites →https://doi.org/10.1109/micro.1997.645806openalex-snapshot
The multicluster architecture: reducing cycle time through partitioning
inferredcites →https://doi.org/10.1109/micro.1998.742779openalex-snapshot
Putting the fill unit to work: dynamic optimizations for trace cache microprocessors
inferredcites →https://doi.org/10.1109/micro.2001.991122openalex-snapshot
Reducing the complexity of the register file in dynamic superscalar processors
inferredcites →https://doi.org/10.1109/micro.2002.1176248openalex-snapshot
Reducing register ports for higher speed and lower energy
inferredcites →https://doi.org/10.1109/micro.2003.1253202openalex-snapshot
Macro-op scheduling: relaxing scheduling loop constraints
inferredcites →https://doi.org/10.1109/pact.2002.1106028openalex-snapshot
Efficient interconnects for clustered microarchitectures
inferredcites →https://doi.org/10.1145/1028176.1006721openalex-snapshot
From Sequences of Dependent Instructions to Functions
inferredcites →https://doi.org/10.1145/144965.145794openalex-snapshot
Interlock collapsing ALU for increased instruction-level parallelism
inferredcites →https://doi.org/10.1145/264107.264201openalex-snapshot
Complexity-effective superscalar processors
inferredcites →https://doi.org/10.1145/268806.268810openalex-snapshot
The SimpleScalar tool set, version 2.0
inferredcites →https://doi.org/10.1145/300979.300995openalex-snapshot
Simultaneous subordinate microthreading (SSMT)
inferredcites →https://doi.org/10.1145/360128.360136openalex-snapshot
On pipelining dynamic instruction scheduling logic
inferredcites →https://doi.org/10.1145/360128.360165openalex-snapshot
Instruction distribution heuristics for quad-cluster, dynamically-scheduled, superscalar processors
inferredcites →https://doi.org/10.1145/545214.545221openalex-snapshot
Efficient dynamic scheduling through tag elimination
inferredcites →https://doi.org/10.1145/545214.545224openalex-snapshot
An instruction set and microarchitecture for instruction level distributed processing
inferredcites →https://doi.org/10.1145/859618.859649openalex-snapshot
Improving dynamic cluster assignment for clustered trace cache processors
inferredcites →https://doi.org/10.5555/290940.290977openalex-snapshot
Putting the fill unit to work: dynamic optimizations for trace cache microprocessors
inferredcites →https://doi.org/10.5555/563998.564029openalex-snapshot
Reducing the complexity of the register file in dynamic superscalar processors
inferredcites →https://doi.org/10.5555/563998.564037openalex-snapshot
Dynamic speculative precomputation
inferredcites →https://doi.org/10.5555/774861.774880openalex-snapshot
Reducing register ports for higher speed and lower energy
inferredcites →https://doi.org/10.5555/956417.956563openalex-snapshot
Macro-op scheduling: relaxing scheduling loop constraints
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Dynamic Instruction Cascading on GALS Microprocessors
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Functional Unit Chaining: A Runtime Adaptive Architecture for Reducing Bypass Delays
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Impact of Software Bypassing on Instruction Level Parallelism and Register File Traffic
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A Simple Mechanism for Collapsing Instructions under Timing Speculation
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An Approach for Implementing Efficient Superscalar CISC Processors
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An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors
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Reducing Operand Communication Overhead using Instruction Clustering for Multimedia Application
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Accelerating Embedded Multimedia Applications with Versatile and Reconfigurable Instruction Fusion
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Amplifying Embedded System Efficiency via Automatic Instruction Fusion on a Post-Manufacturing Reconfigurable Architecture Platform
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Serialization-Aware Mini-Graphs: Performance with Fewer Resources
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A Novel Highly Scalable Architecture with Partially Distributed Pipeline and Hardware/Software Instruction Encoding
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Predicting and Exploiting Transient Values for Reducing Register File Pressure and Energy Consumption
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Achieving Out-of-Order Performance with Almost In-Order Complexity
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Comparing FPGA vs. custom cmos and the impact on processor microarchitecture
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Use of compiler optimization of software bypassing as a method to improve energy efficiency of exposed data path architectures
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A Preliminary Evaluation of Timing-Speculative Instruction Collapsing
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A pattern based instruction encoding technique for high performance architectures
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Dynamic Dependency Collapsing
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Kangaroo: Dynamic Fusion of Branch Instructions in a Pipelined Uniprocessor
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