On the public citation graph
Serialization-Aware Mini-Graphs: Performance with Fewer Resources
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/fpga.1997.624600openalex-snapshot
Garp: a MIPS processor with a reconfigurable coprocessor
inferredcites →https://doi.org/10.1109/hpca.2006.1598111openalex-snapshot
An Approach for Implementing Efficient Superscalar CISC Processors
inferredcites →https://doi.org/10.1109/isca.2000.854393openalex-snapshot
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
inferredcites →https://doi.org/10.1109/ispass.2000.842295openalex-snapshot
CommBench-a telecommunications benchmark for network processors
inferredcites →https://doi.org/10.1109/micro.1997.645830openalex-snapshot
MediaBench: a tool for evaluating and synthesizing multimedia and communications systems
inferredcites →https://doi.org/10.1109/micro.2002.1176235openalex-snapshot
Characterizing and predicting value degree of use
inferredcites →https://doi.org/10.1109/micro.2003.1253189openalex-snapshot
Processor acceleration through automated instruction set customization
inferredcites →https://doi.org/10.1109/micro.2003.1253202openalex-snapshot
Macro-op scheduling: relaxing scheduling loop constraints
inferredcites →https://doi.org/10.1109/micro.2004.15openalex-snapshot
Dataflow Mini-Graphs: Amplifying Superscalar Capacity and Bandwidth
inferredcites →https://doi.org/10.1109/micro.2004.16openalex-snapshot
Dynamic Strands: Collapsing Speculative Dependence Chains for Reducing Pipeline Communication
inferredcites →https://doi.org/10.1109/micro.2004.5openalex-snapshot
Application-Specific Processing on a General-Purpose Core via Transparent Instruction Set Customization
inferredcites →https://doi.org/10.1109/wwc.2001.15openalex-snapshot
MiBench: A free, commercially representative embedded benchmark suite
inferredcites →https://doi.org/10.1109/wwc.2001.990739openalex-snapshot
MiBench: A free, commercially representative embedded benchmark suite
inferredcites →https://doi.org/10.1145/1028176.1006721openalex-snapshot
From Sequences of Dependent Instructions to Functions
inferredcites →https://doi.org/10.1145/298865.298867openalex-snapshot
A text-compression-based method for code size minimization in embedded systems
inferredcites →https://doi.org/10.1145/379240.379253openalex-snapshot
Focusing processor policies via critical-path prediction
inferredcites →https://doi.org/10.1145/545214.545224openalex-snapshot
An instruction set and microarchitecture for instruction level distributed processing
inferredcites →https://doi.org/10.5555/956417.956538openalex-snapshot
Processor acceleration through automated instruction set customization
inferredcites →https://doi.org/10.5555/956417.956563openalex-snapshot
Macro-op scheduling: relaxing scheduling loop constraints
inferredcites →https://doi.org/10.5555/977395.977670openalex-snapshot
Using dynamic binary translation to fuse dependent instructions
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-540-89894-8_33openalex-snapshot
Scalable Multi-cores with Improved Per-core Performance Using Off-the-critical Path Reconfigurable Hardware
inferred← citeshttps://doi.org/10.1007/s10766-010-0128-3openalex-snapshot
Improving Adaptability and Per-Core Performance of Many-Core Processors Through Reconfiguration
inferred← citeshttps://doi.org/10.1109/iccad.2013.6691166openalex-snapshot
A Just-in-Time Customizable processor
inferred← citeshttps://doi.org/10.1109/tvlsi.2008.2000243openalex-snapshot
Selective Writeback: Reducing Register File Pressure and Energy Consumption
inferred← citeshttps://doi.org/10.1109/tvlsi.2025.3592977openalex-snapshot
An Open-Source NanoController v2 Featuring Microcoded Instruction Set Redefinition in 22-nm FDSOI-CMOS for Autonomous Ultralow-Power SoCs
inferred← citeshttps://doi.org/10.1109/vlsi.design.2009.58openalex-snapshot
Improving scalability and per-core performance in multi-cores through resource sharing and reconfiguration
inferred← citeshttps://doi.org/10.1145/1531743.1531768openalex-snapshot
Improving performance of simple cores by exploiting loop-level parallelism through value prediction and reconfiguration
inferred← citeshttps://doi.org/10.1145/1968502.1968510openalex-snapshot
Scientific Application Demands on a Reconfigurable Functional Unit Interface
inferred← citeshttps://doi.org/10.2197/ipsjtrans.2.122openalex-snapshot
An Instruction Scheduler for Dynamic ALU Cascading Adoption
inferred← citeshttps://doi.org/10.5555/1791889.1791928openalex-snapshot
Scalable multi-cores with improved per-core performance using off-the-critical path reconfigurable hardware
inferred← citeshttps://doi.org/10.5555/2561828.2561930openalex-snapshot
A just-in-time customizable processor
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