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Automatic Synthesis of High-Speed Processor Simulators
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-1-4615-1613-2_7openalex-snapshot
Choosing Representative Slices of Program Execution for Microarchitecture Simulations: A Preliminary Application to the Data Stream
inferredcites →https://doi.org/10.1109/12.8699openalex-snapshot
Accurate low-cost methods for performance evaluation of cache memory systems
inferredcites →https://doi.org/10.1109/2.825695openalex-snapshot
PA-RISC to IA-64: transparent execution, no recompilation
inferredcites →https://doi.org/10.1109/2.825696openalex-snapshot
Dynamic and transparent binary translation
inferredcites →https://doi.org/10.1109/2.825697openalex-snapshot
UQBT: adaptable binary translation at low cost
inferredcites →https://doi.org/10.1109/2.982915openalex-snapshot
Rsim: simulating shared-memory multiprocessors with ILP processors
inferredcites →https://doi.org/10.1109/2.982916openalex-snapshot
Simics: A full system simulation platform
inferredcites →https://doi.org/10.1109/2.982917openalex-snapshot
SimpleScalar: an infrastructure for computer system modeling
inferredcites →https://doi.org/10.1109/40.768499openalex-snapshot
An integrated functional performance simulator
inferredcites →https://doi.org/10.1109/hicss.1994.323171openalex-snapshot
Accelerating architectural simulation by parallel execution of trace samples
inferredcites →https://doi.org/10.1109/iccd.1996.563595openalex-snapshot
Reducing state loss for effective trace sampling of superscalar processors
inferredcites →https://doi.org/10.1109/iccd.1996.563597openalex-snapshot
The Augmint multiprocessor simulation toolkit for Intel x86 architectures
inferredcites →https://doi.org/10.1109/iccd.1998.727028openalex-snapshot
The Alpha 21264 microprocessor architecture
inferredcites →https://doi.org/10.1109/iccd.2001.955000openalex-snapshot
Minimal subset evaluation: rapid warm-up for simulated hardware state
inferredcites →https://doi.org/10.1109/ispass.2001.990668openalex-snapshot
MASE: a novel infrastructure for detailed microarchitectural modeling
inferredcites →https://doi.org/10.1109/mascot.1994.284422openalex-snapshot
MINT: a front end for efficient simulation of shared-memory multiprocessors
inferredcites →https://doi.org/10.1109/pact.1998.727263openalex-snapshot
A direct-execution framework for fast and accurate simulation of superscalar processors
inferredcites →https://doi.org/10.1109/pact.2003.1238020openalex-snapshot
Picking statistically valid and early simulation points
inferredcites →https://doi.org/10.1109/shpcc.1994.296728openalex-snapshot
Dynamic program instrumentation for scalable performance tools
inferredcites →https://doi.org/10.1145/183018.183032openalex-snapshot
Shade: a fast instruction-set simulator for execution profiling
inferredcites →https://doi.org/10.1145/183432.183527openalex-snapshot
Optimally profiling and tracing programs
inferredcites →https://doi.org/10.1145/244804.244807openalex-snapshot
Using the SimOS machine simulator to study complex computer systems
inferredcites →https://doi.org/10.1145/268437.268745openalex-snapshot
Efficient instruction cache simulation and execution profiling with a threaded-code interpreter
inferredcites →https://doi.org/10.1145/268806.268810openalex-snapshot
The SimpleScalar tool set, version 2.0
inferredcites →https://doi.org/10.1145/277650.277740openalex-snapshot
Fast, effective code generation in a just-in-time Java compiler
inferredcites →https://doi.org/10.1145/318371.318694openalex-snapshot
Direct execution models of processor behavior and performance
inferredcites →https://doi.org/10.1145/605397.605403openalex-snapshot
Automatically characterizing large scale program behavior
inferredcites →https://doi.org/10.5555/522344.825699openalex-snapshot
An Direct-Execution Framework for Fast and Accurate Simulation of Superscalar Processors
inferredcites →https://doi.org/10.5555/942806.943854openalex-snapshot
Picking statistically valid and early simulation points
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-1-4419-8153-0_3openalex-snapshot
Principles of Design Space Exploration
inferred← citeshttps://doi.org/10.1007/978-1-4419-8255-1openalex-snapshot
Application Analysis Tools for ASIP Design
inferred← citeshttps://doi.org/10.1007/978-1-4614-6859-2_29openalex-snapshot
DSP Instruction Set Simulation
inferred← citeshttps://doi.org/10.1007/978-3-642-22691-5_66openalex-snapshot
Design and Optimization of PowerPC Instruction Set Simulator
inferred← citeshttps://doi.org/10.1016/s0065-2458(08)00004-1openalex-snapshot
Sampled Processor Simulation: A Survey
inferred← citeshttps://doi.org/10.1109/anss.2006.19openalex-snapshot
Design and Implementation of aWorkload Specific Simulator
inferred← citeshttps://doi.org/10.1109/apscc.2012.30openalex-snapshot
A Fast Accurate Interpretive Simulator Based on Shared Basic Block Cache Technique
inferred← citeshttps://doi.org/10.1109/date.2006.244006openalex-snapshot
Constructing Portable Compiled Instruction-set Simulators-An ADL-driven Approach
inferred← citeshttps://doi.org/10.1109/date.2010.5456986openalex-snapshot
Automatic generation of software TLM in multiple abstraction layers for efficient HW/SW co-simulation
inferred← citeshttps://doi.org/10.1109/date.2011.5763060openalex-snapshot
Cycle-count-accurate processor modeling for fast and accurate system-level simulation
inferred← citeshttps://doi.org/10.1109/date.2011.5763061openalex-snapshot
A shared-variable-based synchronization approach to efficient cache coherence simulation for multi-core systems
inferred← citeshttps://doi.org/10.1109/hpec.2012.6408664openalex-snapshot
Fast functional simulation with a dynamic language
inferred← citeshttps://doi.org/10.1109/icie.2009.220openalex-snapshot
SEMCS: A Precise Memory-Hierarchy Simulation Framework on Parallel Full-System Simulator
inferred← citeshttps://doi.org/10.1109/iiswc.2018.8573475openalex-snapshot
Data Motif-based Proxy Benchmarks for Big Data and AI Workloads
inferred← citeshttps://doi.org/10.1109/samos.2015.7363665openalex-snapshot
Efficient dual-ISA support in a retargetable, asynchronous Dynamic Binary Translator
inferred← citeshttps://doi.org/10.1109/vldi-dat.2013.6533806openalex-snapshot
A fast and accurate instruction-oriented processor simulation approach
inferred← citeshttps://doi.org/10.1109/vlsi-soc.2013.6673261openalex-snapshot
A basic-block power annotation approach for fast and accurate embedded software power estimation
inferred← citeshttps://doi.org/10.1109/wscad-ssc.2012.39openalex-snapshot
Optimizing Simulation in Multiprocessor Platforms Using Dynamic-Compiled Simulation
inferred← citeshttps://doi.org/10.1145/1147224.1147225openalex-snapshot
Statistical sampling of microarchitecture simulation
inferred← citeshttps://doi.org/10.1145/1176254.1176302openalex-snapshot
A multiprocessing approach to accelerate retargetable and portable dynamic-compiled instruction-set simulation
inferred← citeshttps://doi.org/10.1145/1176760.1176807openalex-snapshot
High-level power analysis for multi-core chips
inferred← citeshttps://doi.org/10.1145/1289881.1289885openalex-snapshot
A fast and generic hybrid simulation approach using C virtual machine
inferred← citeshttps://doi.org/10.1145/1450135.1450165openalex-snapshot
Simulation and embedded software development for Anton, a parallel machine with heterogeneous multicore ASICs
inferred← citeshttps://doi.org/10.1145/2024724.2024807openalex-snapshot
A high-parallelism distributed scheduling mechanism for multi-core instruction-set simulation
inferred← citeshttps://doi.org/10.1145/2093157.2093161openalex-snapshot
The Java Virtual Machine in retargetable, high-performance instruction set simulation
inferred← citeshttps://doi.org/10.1145/2159542.2159543openalex-snapshot
An Extended SystemC Framework for Efficient HW/SW Co-Simulation
inferred← citeshttps://doi.org/10.1145/2248418.2248422openalex-snapshot
Efficiently parallelizing instruction set simulation of embedded multi-core processors using region-based just-in-time dynamic binary translation
inferred← citeshttps://doi.org/10.1145/2345141.2248422openalex-snapshot
Efficiently parallelizing instruction set simulation of embedded multi-core processors using region-based just-in-time dynamic binary translation
inferred← citeshttps://doi.org/10.1145/2435227.2435250openalex-snapshot
A distributed timing synchronization technique for parallel multi-core instruction-set simulation
inferred← citeshttps://doi.org/10.2200/s00273ed1v01y201006cac010openalex-snapshot
Computer Architecture Performance Evaluation Methods
inferred← citeshttps://doi.org/10.47749/t/unicamp.2011.845811openalex-snapshot
Um simulador compilado dinâmico para o ArchC
inferred← citeshttps://doi.org/10.5555/1870926.1871211openalex-snapshot
Automatic generation of software TLM in multiple abstraction layers for efficient HW/SW co-simulation
inferred← citeshttps://doi.org/10.70675/2c30368ez7cb8z4d3dzb0e4z481762037cd3openalex-snapshot
Simulation Native des Systèmes Multiprocesseurs sur Puce à l'aide de la Virtualisation Assistée par le Matériel
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