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A Survey of Cache Simulators
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-3-319-26362-5_3openalex-snapshot
Reverse Engineering Intel Last-Level Cache Complex Addressing Using Performance Counters
inferredcites →https://doi.org/10.1007/978-3-319-64203-1_9openalex-snapshot
An Accurate Simulator of Cache-Line Conflicts to Exploit the Underlying Cache Performance
inferredcites →https://doi.org/10.1007/978-3-642-04284-3_9openalex-snapshot
Modeling Cache Effects at the Transaction Level
inferredcites →https://doi.org/10.1109/2.869367openalex-snapshot
SPEC CPU2000: measuring CPU performance in the New Millennium
inferredcites →https://doi.org/10.1109/2.982917openalex-snapshot
SimpleScalar: an infrastructure for computer system modeling
inferredcites →https://doi.org/10.1109/40.710872openalex-snapshot
Virtual memory in contemporary microprocessors
inferredcites →https://doi.org/10.1109/access.2019.2917698openalex-snapshot
A Survey of Computer Architecture Simulation Techniques and Tools
inferredcites →https://doi.org/10.1109/aspdac.2015.7059093openalex-snapshot
A trace-driven approach for fast and accurate simulation of manycore architectures
inferredcites →https://doi.org/10.1109/hpca.2010.5416635openalex-snapshot
Graphite: A distributed parallel simulator for multicores
inferredcites →https://doi.org/10.1109/hpca.2011.5749747openalex-snapshot
HAsim: FPGA-based high-detail multicore simulation using time-division multiplexing
inferredcites →https://doi.org/10.1109/isca.1994.288167openalex-snapshot
Proceedings of 21 International Symposium on Computer Architecture
inferredcites →https://doi.org/10.1109/isca.2005.52openalex-snapshot
The V-Way Cache: Demand Based Associativity via Global Replacement
inferredcites →https://doi.org/10.1109/isca.2018.00014openalex-snapshot
FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud
inferredcites →https://doi.org/10.1109/ispass.2007.363733openalex-snapshot
PTLsim: A Cycle Accurate Full System x86-64 Microarchitectural Simulator
inferredcites →https://doi.org/10.1109/ispass.2009.4919638openalex-snapshot
Zesto: A cycle-level simulator for highly detailed microarchitecture exploration
inferredcites →https://doi.org/10.1109/ispass.2010.5452079openalex-snapshot
Dynamic program analysis of Microsoft Windows applications
inferredcites →https://doi.org/10.1109/ispass.2013.6557172openalex-snapshot
Non-determinism and overcount on modern hardware performance counter implementations
inferredcites →https://doi.org/10.1109/ispass.2014.6844457openalex-snapshot
Sources of error in full-system simulation
inferredcites →https://doi.org/10.1109/ispass.2014.6844466openalex-snapshot
Manifold: A parallel simulation framework for multicore systems
inferredcites →https://doi.org/10.1109/ispass.2014.6844475openalex-snapshot
Reverse engineering of cache replacement policies in Intel microprocessors and their evaluation
inferredcites →https://doi.org/10.1109/ispass.2018.00013openalex-snapshot
Hardware-Validated CPU Performance and Energy Modelling
inferredcites →https://doi.org/10.1109/ispass.2019.00014openalex-snapshot
Racing to Hardware-Validated Simulation
inferredcites →https://doi.org/10.1109/mascot.2003.1240655openalex-snapshot
On modeling and analyzing cache hierarchies using CASPER
inferredcites →https://doi.org/10.1109/micro.2004.7openalex-snapshot
Automatic Synthesis of High-Speed Processor Simulators
inferredcites →https://doi.org/10.1109/micro.2010.20openalex-snapshot
The ZCache: Decoupling Ways and Associativity
inferredcites →https://doi.org/10.1109/mm.2006.73openalex-snapshot
IPC Considered Harmful for Multiprocessor Workloads
inferredcites →https://doi.org/10.1109/mm.2007.56openalex-snapshot
Microarchitecture-Independent Workload Characterization
inferredcites →https://doi.org/10.1109/mm.2007.66openalex-snapshot
Exploring Large-Scale CMP Architectures Using ManySim
inferredcites →https://doi.org/10.1109/pact.2003.1237995openalex-snapshot
Proceedings 12th International Conference on Parallel Architectures and Compilation Techniques - PACT 2003
inferredcites →https://doi.org/10.1109/patmos.2015.7347586openalex-snapshot
Tejas: A java based versatile micro-architectural simulator
inferredcites →https://doi.org/10.1109/recosoc.2012.6322869openalex-snapshot
Accuracy evaluation of GEM5 simulator system
inferredcites →https://doi.org/10.1109/tc.2006.44openalex-snapshot
Simulation of computer architectures: simulators, benchmarks, methodologies, and recommendations
inferredcites →https://doi.org/10.1109/tc.2016.2519901openalex-snapshot
TranSim: A Simulation Framework for Cache-Enabled Transparent Computing Systems
inferredcites →https://doi.org/10.1109/tc.2017.2723878openalex-snapshot
Analytical Miss Rate Calculation of L2 Cache from the RD Profile of L1 Cache
inferredcites →https://doi.org/10.1109/tcad.2012.2184760openalex-snapshot
HORNET: A Cycle-Level Multicore Simulator
inferredcites →https://doi.org/10.1109/tcad.2015.2481796openalex-snapshot
Accelerating Architectural Simulation Via Statistical Techniques: A Survey
inferredcites →https://doi.org/10.1109/vlsid.2015.28openalex-snapshot
Can You Trust Your Memory Trace? A Comparison of Memory Traces from Binary Instrumentation and Simulation
inferredcites →https://doi.org/10.1145/1140103.1140303openalex-snapshot
Automatic logging of operating system effects to guide application-level architecture simulation
inferredcites →https://doi.org/10.1145/165123.165152openalex-snapshot
A case for two-way skewed-associative caches
inferredcites →https://doi.org/10.1145/224081.224092openalex-snapshot
Reducing the frequency of tag compares for low power I-cache design
inferredcites →https://doi.org/10.1145/2480741.2480749openalex-snapshot
A survey on cache tuning from a power/energy perspective
inferredcites →https://doi.org/10.1145/2629677openalex-snapshot
An Evaluation of High-Level Mechanistic Core Models
inferredcites →https://doi.org/10.1145/2818353openalex-snapshot
Two-Level Hybrid Sampled Simulation of Multithreaded Applications
inferredcites →https://doi.org/10.1145/3023973.3023974openalex-snapshot
Adaptive Cache Warming for Faster Simulations
inferredcites →https://doi.org/10.1145/800015openalex-snapshot
Proceedings of the 11th annual international symposium on Computer architecture - ISCA '84
inferredcites →https://doi.org/10.1145/980152.980157openalex-snapshot
Temperature-aware microarchitecture
inferredcites →https://doi.org/10.2200/s00273ed1v01y201006cac010openalex-snapshot
Computer Architecture Performance Evaluation Methods
inferredcites →https://doi.org/10.2200/s00345ed1v01y201104cac015openalex-snapshot
Dynamic Binary Modification: Tools, Techniques, and Applications
inferredcites →https://doi.org/10.2200/s00586ed1v01y201407cac029openalex-snapshot
FPGA-Accelerated Simulation of Computer Systems
inferredcites →https://doi.org/10.5120/ijca2016911316openalex-snapshot
A Comparative Study of Heterogeneous Processor Simulators
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-031-83093-8_6openalex-snapshot
Programmable Analysis of RISC-V Processors Using WAL
inferred← citeshttps://doi.org/10.1007/978-981-99-4590-0_2openalex-snapshot
Cache Computing for Dew Devices at the Edge Networks
inferred← citeshttps://doi.org/10.1016/j.comnet.2024.110985openalex-snapshot
VEC-Sim: A simulation platform for evaluating service caching and computation offloading policies in Vehicular Edge Networks
inferred← citeshttps://doi.org/10.1016/j.simpat.2024.103032openalex-snapshot
Survey of CPU and memory simulators in computer architecture: A comprehensive analysis including compiler integration and emerging technology applications
inferred← citeshttps://doi.org/10.1080/17445760.2023.2293913openalex-snapshot
CAMP: a hierarchical cache architecture for multi-core mixed criticality processors
inferred← citeshttps://doi.org/10.1109/candarw53999.2021.00078openalex-snapshot
Thread-Aware Cache Simulator for HPC Application Tuning
inferred← citeshttps://doi.org/10.1109/dsd53832.2021.00024openalex-snapshot
Cache-accel: FPGA Accelerated Cache Simulator with Partially Reconfigurable Prefetcher
inferred← citeshttps://doi.org/10.1109/ewdts52692.2021.9580989openalex-snapshot
Using Architecture Simulation Tool for Memory Subsystem Evaluation in Multi-core Systems
inferred← citeshttps://doi.org/10.1109/fdl63219.2024.10673859openalex-snapshot
An Extensible and Flexible Methodology for Analyzing the Cache Performance of Hardware Designs
inferred← citeshttps://doi.org/10.1109/iccad66269.2025.11240912openalex-snapshot
ScanNow: A Scan Window-Based Sparse Matrix Multiplication Accelerator Design
inferred← citeshttps://doi.org/10.1109/icrtcst54752.2022.9781893openalex-snapshot
Integration of Pycachesim with QEMU
inferred← citeshttps://doi.org/10.1109/isqed51717.2021.9424272openalex-snapshot
FPGA Accelerated Parameterized Cache Simulator
inferred← citeshttps://doi.org/10.1109/lca.2024.3441941openalex-snapshot
Octopus: A Cycle-Accurate Cache System Simulator
inferred← citeshttps://doi.org/10.1109/lca.2025.3592946openalex-snapshot
Camulator: A Lightweight and Extensible Trace-Driven Cache Simulator for Embedded Multicore SoCs
inferred← citeshttps://doi.org/10.1109/tc.2021.3060650openalex-snapshot
Observing the Invisible: Live Cache Inspection for High-Performance Embedded Systems
inferred← citeshttps://doi.org/10.1109/tc.2024.3416747openalex-snapshot
CBANA: A Lightweight, Efficient, and Flexible Cache Behavior Analysis Framework
inferred← citeshttps://doi.org/10.1145/3511094openalex-snapshot
Energy Efficient Computing Systems: Architectures, Abstractions and Modeling to Techniques and Standards
inferred← citeshttps://doi.org/10.1145/3522784.3522801openalex-snapshot
HyCSim: A rapid design space exploration tool for emerging hybrid last-level caches
inferred← citeshttps://doi.org/10.1145/3558003openalex-snapshot
BullsEye : Scalable and Accurate Approximation Framework for Cache Miss Calculation
inferred← citeshttps://doi.org/10.1145/3656012openalex-snapshot
TAO: Re-Thinking DL-based Microarchitecture Simulation
inferred← citeshttps://doi.org/10.1145/3695053.3731037openalex-snapshot
Concorde: Fast and Accurate CPU Performance Modeling with Compositional Analytical-ML Fusion
inferred← citeshttps://doi.org/10.1145/3731599.3767516openalex-snapshot
A Cache Interaction Graph for Data Locality Optimization
inferred← citeshttps://doi.org/10.1145/3743646.3750019openalex-snapshot
VMS: Visual Cache Memory Simulator with Spatio-Temporal Visualization
inferred← citeshttps://doi.org/10.1145/3763790openalex-snapshot
CCKit: An open-source toolkit for cache coherent accelerators
inferred← citeshttps://doi.org/10.48550/arxiv.2005.11357openalex-snapshot
Accelerate Cycle-Level Full-System Simulation of Multi-Core RISC-V Systems with Binary Translation
inferred← citeshttps://doi.org/10.5753/cbie_estendido.2022.226359openalex-snapshot
Beto, o simulador de memória cache
inferred← citeshttps://doi.org/10.5753/wei.2021.15922openalex-snapshot
ECS e EMCS: Simuladores de Caches para o Apoio Pedagógico no Ensino de Arquitetura de Computadores
inferred← citeshttps://doi.org/10.70675/ca3f8996z3f77z44f3zaad4z9695383b3ca8openalex-snapshot
Accurate Simulation of Data Movement in Modern Mobile Multicore Systems
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