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Cherry-MP: Correctly Integrating Checkpointed Early Resource Recycling in Chip Multiprocessors
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/12.509907openalex-snapshot
ARB: a hardware mechanism for dynamic reordering of memory references
inferredcites →https://doi.org/10.1109/12.543705openalex-snapshot
An architecture for tolerating processor failures in shared-memory multiprocessors
inferredcites →https://doi.org/10.1109/12.795218openalex-snapshot
A chip-multiprocessor architecture with speculative multithreading
inferredcites →https://doi.org/10.1109/2.546611openalex-snapshot
Shared memory consistency models: a tutorial
inferredcites →https://doi.org/10.1109/40.491460openalex-snapshot
The Mips R10000 superscalar microprocessor
inferredcites →https://doi.org/10.1109/71.80134openalex-snapshot
Error recovery in shared memory multiprocessors using private caches
inferredcites →https://doi.org/10.1109/ftcs.1990.89338openalex-snapshot
Cache-aided rollback error recovery (CARER) algorithm for shared-memory multiprocessor systems
inferredcites →https://doi.org/10.1109/hpca.1996.501172openalex-snapshot
Register file design considerations in dynamically scheduled processors
inferredcites →https://doi.org/10.1109/hpca.1998.650541openalex-snapshot
The potential for using thread-level data speculation to facilitate automatic parallelization
inferredcites →https://doi.org/10.1109/hpca.1998.650559openalex-snapshot
Speculative versioning cache
inferredcites →https://doi.org/10.1109/hpca.2003.1183532openalex-snapshot
Runahead execution: an alternative to very large instruction windows for out-of-order processors
inferredcites →https://doi.org/10.1109/hpca.2005.9openalex-snapshot
Checkpointed early load retirement
inferredcites →https://doi.org/10.1109/isca.1990.134503openalex-snapshot
Memory consistency and event ordering in scalable shared-memory multiprocessors
inferredcites →https://doi.org/10.1109/isca.1995.524546openalex-snapshot
The SPLASH-2 programs: characterization and methodological considerations
inferredcites →https://doi.org/10.1109/l-ca.2002.8openalex-snapshot
MinneSPEC: A New SPEC Benchmark Workload for Simulation-Based Computer Architecture Research
inferredcites →https://doi.org/10.1109/l-ca.2004.3openalex-snapshot
CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction
inferredcites →https://doi.org/10.1109/mcc.1999.766975openalex-snapshot
Parallel Computer Architecture: A Hardware/Software Approach
inferredcites →https://doi.org/10.1109/micro.2002.1176234openalex-snapshot
Cherry: Checkpointed early resource recycling in out-of-order microprocessors
inferredcites →https://doi.org/10.1109/micro.2003.1253246openalex-snapshot
Checkpoint processing and recovery: towards scalable large instruction window processors
inferredcites →https://doi.org/10.1109/reldis.1994.336910openalex-snapshot
Coordinated checkpointing-rollback error recovery for distributed shared memory multicomputers
inferredcites →https://doi.org/10.1145/1044823.1044825openalex-snapshot
Toward kilo-instruction processors
inferredcites →https://doi.org/10.1145/17356.17404openalex-snapshot
A class of compatible cache consistency protocols and their support by the IEEE futurebus
inferredcites →https://doi.org/10.1145/285930.285997openalex-snapshot
Memory consistency and event ordering in scalable shared-memory multiprocessors
inferredcites →https://doi.org/10.1145/339647.363382openalex-snapshot
Architectural support for scalable speculative parallelization in shared-memory multiprocessors
inferredcites →https://doi.org/10.1145/977091.977120openalex-snapshot
A first glance at Kilo-instruction based multiprocessors
inferredcites →https://doi.org/10.1155/2003/401032openalex-snapshot
Quantitative Performance Analysis of the SPEC OMPM2001 Benchmarks
inferredcites →https://doi.org/10.5555/956417.956554openalex-snapshot
Checkpoint processing and recovery: towards scalable large instruction window processors
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/11945918_18openalex-snapshot
Trade-Offs in Transient Fault Recovery Schemes for Redundant Multithreaded Processors
inferred← citeshttps://doi.org/10.1007/978-3-540-74309-5_32openalex-snapshot
Implicit Transactional Memory in Kilo-Instruction Multiprocessors
inferred← citeshttps://doi.org/10.1016/j.proeng.2011.08.935openalex-snapshot
Bhs: An Novel Scheduling Strategy on Modern Processors
inferred← citeshttps://doi.org/10.1109/date.2010.5457061openalex-snapshot
Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors
inferred← citeshttps://doi.org/10.1109/dsn.2007.100openalex-snapshot
Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor
inferred← citeshttps://doi.org/10.1109/dsn.2010.5544918openalex-snapshot
Energy-efficient fault tolerance in chip multiprocessors using Critical Value Forwarding
inferred← citeshttps://doi.org/10.1109/iccd.2010.5647558openalex-snapshot
Out-of-order retirement of instructions in sequentially consistent multiprocessors
inferred← citeshttps://doi.org/10.1109/isca.2006.13openalex-snapshot
Bulk Disambiguation of Speculative Threads in Multiprocessors
inferred← citeshttps://doi.org/10.1109/isca.2014.6853200openalex-snapshot
Avoiding core's DUE & SDC via acoustic wave detectors and tailored error containment and recovery
inferred← citeshttps://doi.org/10.1109/isie.2012.6237193openalex-snapshot
Block-based hardware scheduler design on Many-core architecture
inferred← citeshttps://doi.org/10.1109/l-ca.2008.12openalex-snapshot
DDMR: Dynamic and Scalable Dual Modular Redundancy with Short Validation Intervals
inferred← citeshttps://doi.org/10.1109/tc.2007.70785openalex-snapshot
Predicting and Exploiting Transient Values for Reducing Register File Pressure and Energy Consumption
inferred← citeshttps://doi.org/10.1109/tc.2009.95openalex-snapshot
A Complexity-Effective Out-of-Order Retirement Microarchitecture
inferred← citeshttps://doi.org/10.1109/tpds.2011.255openalex-snapshot
A Sequentially Consistent Multiprocessor Architecture for Out-of-Order Retirement of Instructions
inferred← citeshttps://doi.org/10.1109/vlsid60093.2024.00067openalex-snapshot
Early Execution for Soft Error Detection
inferred← citeshttps://doi.org/10.1145/1150019.1136506openalex-snapshot
Bulk Disambiguation of Speculative Threads in Multiprocessors
inferred← citeshttps://doi.org/10.1145/1168857.1168868openalex-snapshot
Ultra low-cost defect protection for microprocessor pipelines
inferred← citeshttps://doi.org/10.1145/1168917.1168868openalex-snapshot
Ultra low-cost defect protection for microprocessor pipelines
inferred← citeshttps://doi.org/10.1145/1168918.1168868openalex-snapshot
Ultra low-cost defect protection for microprocessor pipelines
inferred← citeshttps://doi.org/10.1145/1168919.1168868openalex-snapshot
Ultra low-cost defect protection for microprocessor pipelines
inferred← citeshttps://doi.org/10.1145/1582710.1582712openalex-snapshot
Checkpoint allocation and release
inferred← citeshttps://doi.org/10.1145/2678373.2665682openalex-snapshot
Avoiding core's DUE & SDC via acoustic wave detectors and tailored error containment and recovery
inferred← citeshttps://doi.org/10.1145/3725843.3756135openalex-snapshot
ATR: Out-of-Order Register Release Exploiting Atomic Regions
inferred← citeshttps://doi.org/10.4995/thesis/10251/8535openalex-snapshot
Out-of-Order Retirement of Instructions in Superscalar, Multithreaded, and Multicore Processors
inferred← citeshttps://doi.org/10.5821/dissertation-2117-95586openalex-snapshot
Designs for increasing reliability while reducing energy and increasing lifetime
inferred← citeshttps://doi.org/10.5821/dissertation-2117-98119openalex-snapshot
Soft error mitigation techniques for future chip multiprocessors
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