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Bulk Disambiguation of Speculative Threads in Multiprocessors
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/12.509907openalex-snapshot
ARB: a hardware mechanism for dynamic reordering of memory references
inferredcites →https://doi.org/10.1109/12.795219openalex-snapshot
The superthreaded processor architecture
inferredcites →https://doi.org/10.1109/hpca.1998.650541openalex-snapshot
The potential for using thread-level data speculation to facilitate automatic parallelization
inferredcites →https://doi.org/10.1109/hpca.1998.650559openalex-snapshot
Speculative versioning cache
inferredcites →https://doi.org/10.1109/hpca.2006.1598134openalex-snapshot
LogTM: Log-based Transactional Memory
inferredcites →https://doi.org/10.1109/isca.1993.698569openalex-snapshot
Transactional Memory: Architectural Support For Lock-free Data Structures
inferredcites →https://doi.org/10.1109/isca.2004.1310767openalex-snapshot
Transactional memory coherence and consistency
inferredcites →https://doi.org/10.1109/isca.2005.54openalex-snapshot
Virtualizing Transactional Memory
inferredcites →https://doi.org/10.1109/micro.2005.15openalex-snapshot
Cherry-MP: Correctly Integrating Checkpointed Early Resource Recycling in Chip Multiprocessors
inferredcites →https://doi.org/10.1145/1054943.1054953openalex-snapshot
Evaluating kilo-instruction multiprocessors
inferredcites →https://doi.org/10.1145/1088149.1088173openalex-snapshot
Tasking with out-of-order spawn in TLS chip multiprocessors
inferredcites →https://doi.org/10.1145/1089008.1089010openalex-snapshot
Tradeoffs in buffering speculative memory state for thread-level speculation in multiprocessors
inferredcites →https://doi.org/10.1145/277830.277852openalex-snapshot
Hardware and software support for speculative execution of sequential binaries on a chip-multiprocessor
inferredcites →https://doi.org/10.1145/291069.291020openalex-snapshot
Data speculation support for a chip multiprocessor
inferredcites →https://doi.org/10.1145/305138.305214openalex-snapshot
Clustered speculative multithreaded processors
inferredcites →https://doi.org/10.1145/339647.339650openalex-snapshot
A scalable approach to thread-level speculation
inferredcites →https://doi.org/10.1145/342001.363382openalex-snapshot
Architectural support for scalable speculative parallelization in shared-memory multiprocessors
inferredcites →https://doi.org/10.1145/362686.362692openalex-snapshot
Space/time trade-offs in hash coding with allowable errors
inferredcites →https://doi.org/10.1147/sj.442.0399openalex-snapshot
The Jikes Research Virtual Machine project: Building an open-source research community
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Compiler and runtime techniques for software transactional memory optimization
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On the design of energy‐efficient hardware transactional memory systems
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Speculatively Multithreaded Architectures
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Conflict Detection in Hardware Transactional Memory
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Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems
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Application-Specific Signatures for Transactional Memory in Soft Processors
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Interval Filter: A Locality-Aware Alternative to Bloom Filters for Hardware Membership Queries by Interval Classification
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Unified Locality-Sensitive Signatures for Transactional Memory
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Compiler Support for Concurrency Synchronization
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Monitoring Data Structures Using Hardware Transactional Memory
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ByteSTM: Virtual Machine-Level Java Software Transactional Memory
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Partition-Based Hardware Transactional Memory for Many-Core Processors
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Removal of Conflicts in Hardware Transactional Memory Systems
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New Data Structures to Handle Speculative Parallelization at Runtime
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Restart Optimization for Transactional Memory with Lazy Conflict Detection
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Selective dynamic serialization for reducing energy consumption in hardware transactional memory systems
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A priority scheduling for TM pathologies
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Fast and efficient commits for Lazy-Lazy hardware transactional memory
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Leveraging irrevocability to deal with signature saturation in hardware transactional memory
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An analytic framework for performance modeling of software transactional memory
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Efficient execution of speculative threads and transactions with hardware transactional memory
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Embedded-TM: Energy and complexity-effective hardware transactional memory for embedded multicore systems
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Lightweight Transactional Memory systems for NoCs based architectures: Design, implementation and comparison of two policies
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Migration in Hardware Transactional Memory on Asymmetric Multiprocessor
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LogSPoTM: a scalable thread level speculation model based on transactional memory
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Priority-Based Conflict Resolution for Hardware Transactional Memory
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Hardware/hybrid transactional memory
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A Quantitative Analysis about the Cache Set-Level Utilization
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A Scalable, Non-blocking Approach to Transactional Memory
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HARD: Hardware-Assisted Lockset-based Race Detection
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LogTM-SE: Decoupling Hardware Transactional Memory from Caches
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iCFP: Tolerating all-level cache misses in in-order processors
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LiteTM: Reducing transactional state overhead
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π-TM: Pessimistic invalidation for scalable lazy hardware transactional memory
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BulkSMT: Designing SMT processors for atomic-block execution
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Pacman: Tolerating asymmetric data races with unintrusive hardware
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BulkCompactor: Optimized deterministic execution via Conflict-Aware commit of atomic blocks
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High-Performance GPU Transactional Memory via Eager Conflict Detection
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MERCURY: Accelerating DNN Training By Exploiting Input Similarity
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Safety Hints for HTM Capacity Abort Mitigation
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Synthesis from multi-cycle atomic actions as a solution to the timing closure problem
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Hardware support for production run diagnosis of performance bugs
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Conflict detection via adaptive signature for software transactional memory
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Exploring Speculative Procedure Level Parallelism from Multimedia Applications
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An Analysis and a Solution of False Conflicts for Hardware Transactional Memory
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Value Predicted LogSPoTM: Improve the Parallesim of Thread Level System by Using a Value Predictor
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SeTM: Efficient Execution of Speculative Threads with Hardware Transactional Memory
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LV∗: A low complexity lazy versioning HTM infrastructure
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A survey of hardware signature implementations in multi-core systems
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Analysis on semantic transactional memory footprint for hardware transactional memory
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Speculation-based conflict resolution in hardware transactional memory
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Locality-aware adaptive grain signatures for Transactional Memories
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Unified Signatures for Improving Performance in Transactional Memory
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Rethinking Support for Region Conflict Exceptions
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Transaction-Based Core Reliability
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Conflict Avoidance Scheduling Using Grouping List for Transactional Memory
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Flexible Decoupled Transactional Memory Support
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TokenTM: Efficient Execution of Large Transactions with Hardware Transactional Memory
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Rerun: Exploiting Episodes for Lightweight Memory Race Recording
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Atom-Aid: Detecting and Surviving Atomicity Violations
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BlockChop: Dynamic squash elimination for hybrid processor architecture
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HADES: Hardware-Assisted Distributed Transactions in the Age of Fast Networks and SmartNICs
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Implementation of adaptive grain signatures for transactional memories
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Using Transactional Memory to Synchronize an Adaptive Garbage Collector in Real-Time Java
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GCMS: A Global Contention Management Scheme in Hardware Transactional Memory
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Core Reliability: Leveraging Hardware Transactional Memory
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Implementing Signatures for Transactional Memory
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Hardware Support for Relaxed Concurrency Control in Transactional Memory
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AtomTracker: A Comprehensive Approach to Atomic Region Inference and Violation Detection
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Data-centric execution of speculative parallel programs
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Exploiting semantic commutativity in hardware speculation
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Harmonizing Speculative and Non-Speculative Execution in Architectures for Ordered Parallelism
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Performance Pathologies in Hardware Transactional Memory
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Atom-Aid: Detecting and Surviving Atomicity Violations
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Lightweight Transactional Memory systems for large scale shared memory MPSoCs
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tm_db: A Generic Debugging Library for Transactional Programs
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Improving Signatures by Locality Exploitation for Transactional Memory
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Mapping Out a Path from Hardware Transactional Memory to Speculative Multithreading
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SAM: Optimizing Multithreaded Cores for Speculative Parallelism
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Forgive-TM: Supporting Lazy Conflict Detection In Eager Hardware Transactional Memory
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Multiversioned Page Overlays: Enabling Faster Serializable Hardware Transactional Memory
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Characterization of Conflicts in Log-Based Transactional Memory (LogTM)
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Dynamic Serialization: Improving Energy Consumption in Eager-Eager Hardware Transactional Memory Systems
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Classification and Elimination of Conflicts in Hardware Transactional Memory Systems
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Multi-dimensional Evaluation of Haswell's Transactional Memory Performance
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Scalability Analysis of Signatures in Transactional Memory Systems
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Improving Signature Behavior by Irrevocability in Transactional Memory Systems
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Software-Based Cache Coherence with Hardware-Assisted Selective Self-Invalidations Using Bloom Filters
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LS-Sig: Locality-Sensitive Signatures for Transactional Memory
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A Direct Coherence Protocol for Many-Core Chip Multiprocessors
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Efficient Eager Management of Conflicts for Scalable Hardware Transactional Memory
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Hardware Signature Designs to Deal with Asymmetry in Transactional Data Sets
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Improving Utilization of Hardware Signatures in Transactional Memory
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ZEBRA: Data-Centric Contention Management in Hardware Transactional Memory
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TC-Release++: An Efficient Timestamp-Based Coherence Protocol for Many-Core Architectures
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Making the fast case common and the uncommon case simple in unbounded transactional memory
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An effective hybrid transactional memory system with strong isolation guarantees
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Performance pathologies in hardware transactional memory
inferred← citeshttps://doi.org/10.1145/1273440.1250667openalex-snapshot
Making the fast case common and the uncommon case simple in unbounded transactional memory
inferred← citeshttps://doi.org/10.1145/1273440.1250673openalex-snapshot
An effective hybrid transactional memory system with strong isolation guarantees
inferred← citeshttps://doi.org/10.1145/1273440.1250674openalex-snapshot
Performance pathologies in hardware transactional memory
inferred← citeshttps://doi.org/10.1145/1353522.1353527openalex-snapshot
The potential for variable-granularity access tracking for optimistic parallelism
inferred← citeshttps://doi.org/10.1145/1394608.1382134openalex-snapshot
Flexible Decoupled Transactional Memory Support
inferred← citeshttps://doi.org/10.1145/1400214.1400228openalex-snapshot
Software transactional memory
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Scalable and reliable communication for hardware transactional memory
inferred← citeshttps://doi.org/10.1145/1454456.1454466openalex-snapshot
Software Transactional Memory: Why Is It Only a Research Toy?
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Maximum benefit from a minimal HTM
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Maximum benefit from a minimal HTM
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Fast memory snapshot for concurrent programmingwithout synchronization
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Refereeing conflicts in hardware transactional memory
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Parallelizing sequential applications on commodity hardware using a low-cost software transactional memory
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Parallelizing sequential applications on commodity hardware using a low-cost software transactional memory
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A lightweight in-place implementation for software thread-level speculation
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The Bulk Multicore architecture for improved programmability
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Proactive transaction scheduling for contention management
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Architecting a chunk-based memory race recorder in modern CMPs
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Runtime parallelization of legacy code on a transactional memory system
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Efficient processor support for DRFx, a memory model with exceptions
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Efficient processor support for DRFx, a memory model with exceptions
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Efficient processor support for DRFx, a memory model with exceptions
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Global productiveness propagation
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Understanding bloom filter intersection for lazy address-set disambiguation
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Transactional conflict decoupling and value prediction
inferred← citeshttps://doi.org/10.1145/1995896.1995905openalex-snapshot
Multiset signatures for transactional memory
inferred← citeshttps://doi.org/10.1145/2000832.2000833openalex-snapshot
Application-specific signatures for transactional memory in soft processors
inferred← citeshttps://doi.org/10.1145/2016603.1967700openalex-snapshot
Global productiveness propagation
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Complementing user-level coarse-grain parallelism with implicit speculative parallelism
inferred← citeshttps://doi.org/10.1145/2155620.2155655openalex-snapshot
Hardware transactional memory for GPU architectures
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Efficient and accurate data dependence profiling using software signatures
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Hardware support for enforcing isolation in lock-based parallel programs
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An integrated pseudo-associativity and relaxed-order approach to hardware transactional memory
inferred← citeshttps://doi.org/10.1145/2528521.1508262openalex-snapshot
Maximum benefit from a minimal HTM
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Energy efficient GPU transactional memory via space-time optimizations
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Consolidated conflict detection for hardware transactional memory
inferred← citeshttps://doi.org/10.1145/2814270.2814285openalex-snapshot
Runtime pointer disambiguation
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Compiler-Driven Software Speculation for Thread-Level Parallelism
inferred← citeshttps://doi.org/10.1145/2830772.2830777openalex-snapshot
A scalable architecture for ordered parallelism
inferred← citeshttps://doi.org/10.1145/2858965.2814285openalex-snapshot
Runtime pointer disambiguation
inferred← citeshttps://doi.org/10.1145/2938369openalex-snapshot
A Survey on Thread-Level Speculation Techniques
inferred← citeshttps://doi.org/10.1145/2967938.2967959openalex-snapshot
Speculatively Exploiting Cross-Invocation Parallelism
inferred← citeshttps://doi.org/10.1145/3020078.3021743openalex-snapshot
FPGA-Accelerated Transactional Execution of Graph Workloads
inferred← citeshttps://doi.org/10.1145/3079079.3079098openalex-snapshot
Simplification and runtime resolution of data dependence constraints for loop transformations
inferred← citeshttps://doi.org/10.1145/3139461openalex-snapshot
Automatically accelerating non-numerical programs by architecture-compiler co-design
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