On the public citation graph
CAPSULE: Hardware-Assisted Parallel Execution of Component-Based Programs
0 signed · 74 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-1-4302-0358-2_11openalex-snapshot
Language-Oriented Programming
inferredcites →https://doi.org/10.1007/978-1-4757-3472-0_10openalex-snapshot
Monitors: An Operating System Structuring Concept
inferredcites →https://doi.org/10.1007/978-1-4842-1374-2_11openalex-snapshot
Language-Oriented Programming
inferredcites →https://doi.org/10.1109/hpca.1999.744326openalex-snapshot
Supporting fine-grained synchronization on a simultaneous multithreading processor
inferredcites →https://doi.org/10.1109/hpca.2001.903250openalex-snapshot
Speculative data-driven multithreading
inferredcites →https://doi.org/10.1109/isca.1995.524578openalex-snapshot
Simultaneous multithreading: Maximizing on-chip parallelism
inferredcites →https://doi.org/10.1109/isca.2004.1310767openalex-snapshot
Transactional memory coherence and consistency
inferredcites →https://doi.org/10.1109/isca.2006.31openalex-snapshot
Program Demultiplexing: Data-flow based Speculative Parallelization of Methods in Sequential Programs
inferredcites →https://doi.org/10.1109/micro.2004.8openalex-snapshot
Balanced Multithreading: Increasing Throughput via a Low Cost Multithreading Hierarchy
inferredcites →https://doi.org/10.1109/mm.2003.1261386openalex-snapshot
Exploiting ILP, TLP, and DLP with the polymorphous trips architecture
inferredcites →https://doi.org/10.1109/mm.2006.27openalex-snapshot
Wish Branches: Enabling Adaptive and Aggressive Predicated Execution
inferredcites →https://doi.org/10.1145/1028176.1006711openalex-snapshot
Transactional Memory Coherence and Consistency
inferredcites →https://doi.org/10.1145/1028176.1006733openalex-snapshot
Evaluation of the Raw Microprocessor
inferredcites →https://doi.org/10.1145/1065944.1065964openalex-snapshot
Exposing speculative thread parallelism in SPEC2000
inferredcites →https://doi.org/10.1145/1105734.1105742openalex-snapshot
Hardware-modulated parallelism in chip multiprocessors
inferredcites →https://doi.org/10.1145/169627.169724openalex-snapshot
Parallel programming in Split-C
inferredcites →https://doi.org/10.1145/224170.224337openalex-snapshot
Detecting coarse-grain parallelism using an interprocedural parallelizing compiler
inferredcites →https://doi.org/10.1145/263326.263382openalex-snapshot
Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading
inferredcites →https://doi.org/10.1145/339647.339650openalex-snapshot
A scalable approach to thread-level speculation
inferredcites →https://doi.org/10.1145/511334.511343openalex-snapshot
Symbiotic jobscheduling with priorities for a simultaneous multithreading processor
inferredcites →https://doi.org/10.1145/564983.564984openalex-snapshot
Integrating object-oriented programming and protected objects in Ada 95
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-1-4419-6460-1openalex-snapshot
Multiprocessor System-on-Chip
inferred← citeshttps://doi.org/10.1007/978-1-4419-6460-1_3openalex-snapshot
Hardware Support for Efficient Resource Utilization in Manycore Processor Systems
inferred← citeshttps://doi.org/10.1007/978-3-642-00722-4_7openalex-snapshot
Exploiting Speculative TLP in Recursive Programs by Dynamic Thread Prediction
inferred← citeshttps://doi.org/10.1007/978-3-642-03138-0_9openalex-snapshot
Implementing Fine/Medium Grained TLP Support in a Many-Core Architecture
inferred← citeshttps://doi.org/10.1007/978-3-642-24568-8_15openalex-snapshot
An Efficient and Flexible Task Management for Many Cores
inferred← citeshttps://doi.org/10.1007/s11390-009-9295-3openalex-snapshot
Godson-T: An Efficient Many-Core Architecture for Parallel Program Executions
inferred← citeshttps://doi.org/10.1007/s11390-014-1482-1openalex-snapshot
A Static Greedy and Dynamic Adaptive Thread Spawning Approach for Loop-Level Parallelism
inferred← citeshttps://doi.org/10.1016/j.sysarc.2015.01.002openalex-snapshot
FASA: A software architecture and runtime framework for flexible distributed automation systems
inferred← citeshttps://doi.org/10.1109/asap.2011.6043240openalex-snapshot
Decentralized dynamic resource management support for massively parallel processor arrays
inferred← citeshttps://doi.org/10.1109/date.2008.4484767openalex-snapshot
A Practical Approach for Reconciling High and Predictable Performance in Non-Regular Parallel Programs
inferred← citeshttps://doi.org/10.1109/etfa.2013.6647998openalex-snapshot
Reconciling flexibility and robustness in industrial automation systems, and living happily ever after
inferred← citeshttps://doi.org/10.1109/etfa.2014.7005075openalex-snapshot
Disruption-free software updates in automation systems
inferred← citeshttps://doi.org/10.1109/fpl.2014.6927485openalex-snapshot
TransPar: Transformation based dynamic Parallelism for low power CGRAs
inferred← citeshttps://doi.org/10.1109/fpt.2009.5377633openalex-snapshot
FPGA implementation of an invasive computing architecture
inferred← citeshttps://doi.org/10.1109/iiswc.2008.4636091openalex-snapshot
Characterizing and improving the performance of Intel Threading Building Blocks
inferred← citeshttps://doi.org/10.1109/ipdps.2011.157openalex-snapshot
Distributed Resource Reservation in Massively Parallel Processor Arrays
inferred← citeshttps://doi.org/10.1109/ipdps.2011.50openalex-snapshot
A Very Fast Simulator for Exploring the Many-Core Future
inferred← citeshttps://doi.org/10.1109/mm.2012.32openalex-snapshot
Godson-T: An Efficient Many-Core Processor Exploring Thread-Level Parallelism
inferred← citeshttps://doi.org/10.1109/patmos.2016.7833431openalex-snapshot
TransMem: A memory architecture to support dynamic remapping and parallelism in low power high performance CGRAs
inferred← citeshttps://doi.org/10.1109/samos.2013.6621112openalex-snapshot
Energy-aware-task-parallelism for efficient dynamic voltage, and frequency scaling, in CGRAs
inferred← citeshttps://doi.org/10.1109/tc.2012.41openalex-snapshot
SEED: A Statically Greedy and Dynamically Adaptive Approach for Speculative Loop Execution
inferred← citeshttps://doi.org/10.1109/tc.2016.2525981openalex-snapshot
TransMap: Transformation Based Remapping and Parallelism for High Utilization and Energy Efficiency in CGRAs
inferred← citeshttps://doi.org/10.1109/vlsisoc.2009.6041331openalex-snapshot
FSM-controlled architectures for linear invasion
inferred← citeshttps://doi.org/10.1145/1403375.1403555openalex-snapshot
A practical approach for reconciling high and predictable performance in non-regular parallel programs
inferred← citeshttps://doi.org/10.1145/1555754.1555792openalex-snapshot
Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors
inferred← citeshttps://doi.org/10.1145/1555815.1555792openalex-snapshot
Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors
inferred← citeshttps://doi.org/10.1145/1854273.1854297openalex-snapshot
Scalable hardware support for conditional parallelization
inferred← citeshttps://doi.org/10.1145/1988932.1988941openalex-snapshot
Resource-aware programming and simulation of MPSoC architectures through extension of X10
inferred← citeshttps://doi.org/10.1145/2390191.2390193openalex-snapshot
Hierarchical power management for adaptive tightly-coupled processor arrays
inferred← citeshttps://doi.org/10.1145/2584660openalex-snapshot
Invasive Tightly-Coupled Processor Arrays
inferred← citeshttps://doi.org/10.1145/2700250openalex-snapshot
Architecture and Implementation of Dynamic Parallelism, Voltage and Frequency Scaling (PVFS) on CGRAs
inferred← citeshttps://doi.org/10.2991/aest-16.2016.72openalex-snapshot
The application of component dynamic scheduling technology in the automotive network control
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.