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Balanced Multithreading: Increasing Throughput via a Low Cost Multithreading Hierarchy

https://doi.org/10.1109/micro.2004.8
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-3-540-39707-6_6openalex-snapshot
Improving Memory Latency Aware Fetch Policies for SMT Processors
inferredcites →https://doi.org/10.1007/bfb0024207openalex-snapshot
Evaluation of multithreaded processors and thread-switch policies
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Sparcle: an evolutionary processor design for large-scale multiprocessors
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The Mips R10000 superscalar microprocessor
inferredcites →https://doi.org/10.1109/71.798316openalex-snapshot
Software-directed register deallocation for simultaneous multithreaded processors
inferredcites →https://doi.org/10.1109/hpca.2000.824344openalex-snapshot
Software-controlled multithreading using informing memory operations
inferredcites →https://doi.org/10.1109/hpca.2002.995719openalex-snapshot
Loose loops sink chips
inferredcites →https://doi.org/10.1109/hpca.2003.1183521openalex-snapshot
Mini-threads: increasing TLP on small-scale SMT processors
inferredcites →https://doi.org/10.1109/isca.1992.753311openalex-snapshot
An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads
inferredcites →https://doi.org/10.1109/isca.1995.524578openalex-snapshot
Simultaneous multithreading: Maximizing on-chip parallelism
inferredcites →https://doi.org/10.1109/micro.2001.991122openalex-snapshot
Reducing the complexity of the register file in dynamic superscalar processors
inferredcites →https://doi.org/10.1109/micro.2001.991129openalex-snapshot
Handling long-latency loads in a simultaneous multithreading processor
inferredcites →https://doi.org/10.1109/micro.2002.1176248openalex-snapshot
Reducing register ports for higher speed and lower energy
inferredcites →https://doi.org/10.1145/139669.139710openalex-snapshot
An elementary processor architecture with simultaneous instruction issuing from multiple threads
inferredcites →https://doi.org/10.1145/143365.143540openalex-snapshot
Closing the window of vulnerability in multiphase memory transactions
inferredcites →https://doi.org/10.1145/165123.165148openalex-snapshot
Register relocation
inferredcites →https://doi.org/10.1145/195473.195576openalex-snapshot
Interleaving
inferredcites →https://doi.org/10.1145/195473.195583openalex-snapshot
The effectiveness of multiple hardware contexts
inferredcites →https://doi.org/10.1145/223982.224449openalex-snapshot
Simultaneous multithreading
inferredcites →https://doi.org/10.1145/232973.232993openalex-snapshot
Exploiting choice
inferredcites →https://doi.org/10.1145/232973.233000openalex-snapshot
Informing memory operations
inferredcites →https://doi.org/10.1145/2591635.2667161openalex-snapshot
The Tera computer system
inferredcites →https://doi.org/10.1145/339647.339708openalex-snapshot
Multiple-banked register file architectures
inferredcites →https://doi.org/10.1145/342001.339708openalex-snapshot
Multiple-banked register file architectures
inferredcites →https://doi.org/10.1145/356989.357011openalex-snapshot
Symbiotic jobscheduling for a simultaneous mutlithreading processor
inferredcites →https://doi.org/10.1145/378993.379244openalex-snapshot
Symbiotic jobscheduling for a simultaneous multithreaded processor
inferredcites →https://doi.org/10.1145/605397.605403openalex-snapshot
Automatically characterizing large scale program behavior
inferredcites →https://doi.org/10.1145/633625.52449openalex-snapshot
MASA: a multithreaded processor architecture for parallel symbolic computing
inferredcites →https://doi.org/10.1145/77726.255132openalex-snapshot
The Tera computer system
inferredcites →https://doi.org/10.1145/782814.782839openalex-snapshot
Reducing register ports using delayed write-back queues and operand pre-fetch
inferredcites →https://doi.org/10.1145/782837.782839openalex-snapshot
Reducing register ports using delayed write-back queues and operand pre-fetch
inferredcites →https://doi.org/10.1145/859618.859627openalex-snapshot
Banked multiported register files for high-frequency superscalar microprocessors
inferredcites →https://doi.org/10.1145/97444.97683openalex-snapshot
Analysis of multithreaded architectures for parallel computing
inferredcites →https://doi.org/10.1147/rd.446.0885openalex-snapshot
A multithreaded PowerPC processor for commercial servers
inferredcites →https://doi.org/10.5555/224659.224682openalex-snapshot
Increasing superscalar performance through multistreaming
inferredcites →https://doi.org/10.5555/563998.564029openalex-snapshot
Reducing the complexity of the register file in dynamic superscalar processors
inferredcites →https://doi.org/10.5555/563998.564038openalex-snapshot
Handling long-latency loads in a simultaneous multithreading processor
inferredcites →https://doi.org/10.5555/774861.774880openalex-snapshot
Reducing register ports for higher speed and lower energy
inferredcites →https://doi.org/10.7551/mitpress/5239.003.0006openalex-snapshot
The Architecture of HEP

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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A Multithreaded Multicore System for Embedded Media Processing
inferred← citeshttps://doi.org/10.1007/s11241-018-9298-7openalex-snapshot
Analysis of preemption costs for the stack cache
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An instruction-systolic programmable shader architecture for multi-threaded 3D graphics processing
inferred← citeshttps://doi.org/10.1016/j.sysarc.2012.11.005openalex-snapshot
An effective cache scheduling scheme for improving the performance in multi-threaded processors
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A QoS Guaranteed Cache Design for Environment Friendly Computing
inferred← citeshttps://doi.org/10.1109/hpca.2007.346201openalex-snapshot
A Memory-Level Parallelism Aware Fetch Policy for SMT Processors
inferred← citeshttps://doi.org/10.1109/hpca.2011.5749728openalex-snapshot
Fast thread migration via cache working set prediction
inferred← citeshttps://doi.org/10.1109/hpca.2013.6522309openalex-snapshot
RECAP: A region-based cure for the common cold (cache)
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inferred← citeshttps://doi.org/10.1109/hpca47549.2020.00026openalex-snapshot
Q-Zilla: A Scheduling Framework and Core Microarchitecture for Tail-Tolerant Microservices
inferred← citeshttps://doi.org/10.1109/icpp.2009.48openalex-snapshot
Thread Merging Schemes for Multithreaded Clustered VLIW Processors
inferred← citeshttps://doi.org/10.1109/icpp.2015.71openalex-snapshot
Software-Based Lightweight Multithreading to Overlap Memory-Access Latencies of Commodity Processors
inferred← citeshttps://doi.org/10.1109/icsamos.2008.4664864openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/iiswc66894.2025.00014openalex-snapshot
The Fake-Busy and True-Idle Problems of Running Graph Applications on Chiplet-Based Multi-Cores
inferred← citeshttps://doi.org/10.1109/iwias.2006.36openalex-snapshot
Responsive Multithreaded Processor for Distributed Real-Time Processing
inferred← citeshttps://doi.org/10.1109/mascot.2005.69openalex-snapshot
Statistical simulation of multithreaded architectures
inferred← citeshttps://doi.org/10.1109/mascots.2005.68openalex-snapshot
Statistical Simulation of Multithreaded Architectures
inferred← citeshttps://doi.org/10.1109/micro.2006.13openalex-snapshot
CAPSULE: Hardware-Assisted Parallel Execution of Component-Based Programs
inferred← citeshttps://doi.org/10.1109/micro.2006.25openalex-snapshot
Fairness and Throughput in Switch on Event Multithreading
inferred← citeshttps://doi.org/10.1109/newcas.2005.1496686openalex-snapshot
Thread Scheduling Based on Low-Quality Instruction-Prediction for Simultaneous Multithreaded Processors
inferred← citeshttps://doi.org/10.1109/rtas.2007.28openalex-snapshot
Prioritized SMT Architecture with IPC Control Method for Real-Time Processing
inferred← citeshttps://doi.org/10.1109/rtcsa.2010.33openalex-snapshot
Using SMT to Hide Context Switch Times of Large Real-Time Tasksets
inferred← citeshttps://doi.org/10.1109/tc.2010.62openalex-snapshot
On the Problem of Evaluating the Performance of Multiprogrammed Workloads
inferred← citeshttps://doi.org/10.1109/tc.2021.3086069openalex-snapshot
VMT: Virtualized Multi-Threading for Accelerating Graph Workloads on Commodity Processors
inferred← citeshttps://doi.org/10.1109/tvlsi.2010.2064185openalex-snapshot
Reducing Power in All Major CAM and SRAM-Based Processor Units via Centralized, Dynamic Resource Size Management
inferred← citeshttps://doi.org/10.1145/1275937.1275939openalex-snapshot
Fairness enforcement in switch on event multithreading
inferred← citeshttps://doi.org/10.1145/1375527.1375541openalex-snapshot
The shared-thread multiprocessor
inferred← citeshttps://doi.org/10.1145/1509864.1509867openalex-snapshot
Memory-level parallelism aware fetch policies for simultaneous multithreading processors
inferred← citeshttps://doi.org/10.1145/1629395.1629403openalex-snapshot
Hybrid multithreading for VLIW processors
inferred← citeshttps://doi.org/10.1145/2000064.2000093openalex-snapshot
Energy-efficient mechanisms for managing thread context in throughput processors
inferred← citeshttps://doi.org/10.1145/2024723.2000093openalex-snapshot
Energy-efficient mechanisms for managing thread context in throughput processors
inferred← citeshttps://doi.org/10.1145/2166879.2166882openalex-snapshot
A Hierarchical Thread Scheduler and Register File for Energy-Efficient Throughput Processors
inferred← citeshttps://doi.org/10.1145/2834848.2834861openalex-snapshot
Efficient context switching for the stack cache
inferred← citeshttps://doi.org/10.1145/3830418.3843863openalex-snapshot
Computation Is Fast, Use T hreadlet !: Efficient Threading for μs-Scale Computing via OS/Hardware Co-Design
inferred← citeshttps://doi.org/10.2200/s00458ed1v01y201212cac021openalex-snapshot
Multithreading Architecture
inferred← citeshttps://doi.org/10.3233/emc-2006-00027openalex-snapshot
A dynamically reconfigurable cache for multithreaded processors
inferred← citeshttps://doi.org/10.5821/dissertation-2117-93333openalex-snapshot
Runahead threads
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Timing analysis for time-predictable architectures
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Datacenter Architectures for the Microservices Era
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