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In-Network Cache Coherence
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-1-4615-3604-8_12openalex-snapshot
The SCI Cache Coherence Protocol
inferredcites →https://doi.org/10.1016/0026-2692(93)90111-qopenalex-snapshot
Computer architecture: a quantitative approach
inferredcites →https://doi.org/10.1109/12.392846openalex-snapshot
Performance evaluation of the slotted ring multiprocessor
inferredcites →https://doi.org/10.1109/12.752665openalex-snapshot
Exploiting the benefits of multiple-path network in DSM systems: architectural alternatives and performance evaluation
inferredcites →https://doi.org/10.1109/2.546611openalex-snapshot
Shared memory consistency models: a tutorial
inferredcites →https://doi.org/10.1109/40.988687openalex-snapshot
The Alpha 21364 network architecture
inferredcites →https://doi.org/10.1109/his.2001.946702openalex-snapshot
The Alpha 21364 network architecture
inferredcites →https://doi.org/10.1109/hpca.2000.824356openalex-snapshot
The effect of network total order, broadcast, and remote-write capability on network-based shared memory computing
inferredcites →https://doi.org/10.1109/hpca.2001.903255openalex-snapshot
A new scalable directory architecture for large-scale multiprocessors
inferredcites →https://doi.org/10.1109/hpca.2001.903268openalex-snapshot
A delay model and speculative architecture for pipelined routers
inferredcites →https://doi.org/10.1109/icpp.1996.537154openalex-snapshot
Reducing cache invalidation overheads in wormhole routed DSMs using multidestination message passing
inferredcites →https://doi.org/10.1109/isca.1988.5238openalex-snapshot
An evaluation of directory schemes for cache coherence
inferredcites →https://doi.org/10.1109/isca.1988.5253openalex-snapshot
The Wisconsin Multicube: a new large-scale cache-coherent multiprocessor
inferredcites →https://doi.org/10.1109/isca.2000.854398openalex-snapshot
Piranha: a scalable architecture based on single-chip multiprocessing
inferredcites →https://doi.org/10.1109/isca.2005.53openalex-snapshot
Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors
inferredcites →https://doi.org/10.1109/mm.2002.997877openalex-snapshot
The Raw microprocessor: a computational fabric for software circuits and general-purpose programs
inferredcites →https://doi.org/10.1109/mm.2004.88openalex-snapshot
Speculative incoherent cache protocols
inferredcites →https://doi.org/10.1109/spdp.1992.242703openalex-snapshot
The Scalable Tree Protocol-a cache coherence approach for large-scale multiprocessors
inferredcites →https://doi.org/10.1109/tc.1979.1675439openalex-snapshot
How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs
inferredcites →https://doi.org/10.1145/1105734.1105742openalex-snapshot
Hardware-modulated parallelism in chip multiprocessors
inferredcites →https://doi.org/10.1145/1150019.1136515openalex-snapshot
Interconnect-Aware Coherence Protocols for Chip Multiprocessors
inferredcites →https://doi.org/10.1145/237578.237583openalex-snapshot
The GLOW cache coherence protocol extensions for widely shared data
inferredcites →https://doi.org/10.1145/285930.285995openalex-snapshot
An evaluation of directory schemes for cache coherence
inferredcites →https://doi.org/10.1145/300979.301004openalex-snapshot
Multicast snooping: a new coherence method using a multicast address network
inferredcites →https://doi.org/10.1145/379189.379198openalex-snapshot
Two economical directory schemes for large-scale cache coherent multiprocessors
inferredcites →https://doi.org/10.1145/633625.52447openalex-snapshot
The Wisconsin multicube: a new large-scale cache-coherent multiprocessor
inferredcites →https://doi.org/10.1145/74925.74944openalex-snapshot
Introducing memory into the switch elements of multiprocessor interconnection networks
inferredcites →https://doi.org/10.5555/326350.326357openalex-snapshot
Bochs: A Portable PC Emulator for Unix/X
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Adaptive Data Compression for Low-Power On-Chip Networks
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NoC-Based System Integration
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Multi-Core Cache Hierarchies
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Concerning with On-Chip Network Features to Improve Cache Coherence Protocols for CMPs
inferred← citeshttps://doi.org/10.1007/978-3-540-92990-1_27openalex-snapshot
In-Network Caching for Chip Multiprocessors
inferred← citeshttps://doi.org/10.1007/978-3-642-54420-0_47openalex-snapshot
A Lightweight Network of IDs to Quickly Deliver Simple Control Messages
inferred← citeshttps://doi.org/10.1007/s10617-010-9050-6openalex-snapshot
Evaluation of the implementation cost of cache coherence protocols using omniscient actions
inferred← citeshttps://doi.org/10.1007/s10766-013-0247-8openalex-snapshot
Bandwidth Adaptive Cache Coherence Optimizations for Chip Multiprocessors
inferred← citeshttps://doi.org/10.1007/s10766-014-0339-0openalex-snapshot
Cluster Cache Monitor: Leveraging the Proximity Data in CMP
inferred← citeshttps://doi.org/10.1007/s11227-012-0865-8openalex-snapshot
Design and formal verification of a hierarchical cache coherence protocol for NoC based multiprocessors
inferred← citeshttps://doi.org/10.1007/s11227-015-1608-4openalex-snapshot
Locality-aware data replication in the last-level cache for large scale multicores
inferred← citeshttps://doi.org/10.1007/s11390-010-9321-5openalex-snapshot
Hierarchical Cache Directory for CMP
inferred← citeshttps://doi.org/10.1007/s11390-010-9322-4openalex-snapshot
CCNoC: Cache-Coherent Network on Chip for Chip Multiprocessors
inferred← citeshttps://doi.org/10.1016/j.sysarc.2013.06.002openalex-snapshot
Efficient multicast schemes for 3-D Networks-on-Chip
inferred← citeshttps://doi.org/10.1049/iet-cdt.2012.0056openalex-snapshot
Built‐in fast gather control network for efficient support of coherence protocols
inferred← citeshttps://doi.org/10.1109/3pgcic.2013.111openalex-snapshot
Multicast Distribution System with Functions of Time-Shift and Loss-Recovery Based on In-Network Caching and OpenFlow Control
inferred← citeshttps://doi.org/10.1109/access.2023.3234933openalex-snapshot
NCDE: In-Network Caching for Directory Entries to Expedite Data Access in Tiled-Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/ccece.2011.6030618openalex-snapshot
Directory-based cache coherence protocol for power-aware chip-multiprocessors
inferred← citeshttps://doi.org/10.1109/date.2008.4484811openalex-snapshot
Comparison of memory write policies for NoC based Multicore Cache Coherent Systems
inferred← citeshttps://doi.org/10.1109/date.2009.5090820openalex-snapshot
Latency criticality aware on-chip communication
inferred← citeshttps://doi.org/10.1109/dsd.2009.220openalex-snapshot
A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoC
inferred← citeshttps://doi.org/10.1109/dsd.2013.16openalex-snapshot
Interaction of NoC Design and Coherence Protocol in 3D-Stacked CMPs
inferred← citeshttps://doi.org/10.1109/dtis.2009.4938037openalex-snapshot
Towards hierarchical cluster based cache coherence for large-scale network-on-chip
inferred← citeshttps://doi.org/10.1109/em-com.2009.5402983openalex-snapshot
Network Victim Cache: Leveraging Network-on-Chip for Managing Shared Caches in Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/hpca.2007.346210openalex-snapshot
An Adaptive Cache Coherence Protocol Optimized for Producer-Consumer Sharing
inferred← citeshttps://doi.org/10.1109/hpca.2008.4658641openalex-snapshot
Performance and power optimization through data compression in Network-on-Chip architectures
inferred← citeshttps://doi.org/10.1109/hpca.2009.4798238openalex-snapshot
In-Network Snoop Ordering (INSO): Snoopy coherence on unordered interconnects
inferred← citeshttps://doi.org/10.1109/hpca.2014.6835921openalex-snapshot
Locality-aware data replication in the Last-Level Cache
inferred← citeshttps://doi.org/10.1109/hpca.2015.7056032openalex-snapshot
Hierarchical private/shared classification: The key to simple and efficient coherence for clustered cache hierarchies
inferred← citeshttps://doi.org/10.1109/hpca.2018.00012openalex-snapshot
iNPG: Accelerating Critical Section Access with In-network Packet Generation for NoC Based Many-Cores
inferred← citeshttps://doi.org/10.1109/iccd.2013.6657050openalex-snapshot
Bayesian theory oriented Optimal Data-Provider Selection for CMP
inferred← citeshttps://doi.org/10.1109/iccd50377.2020.00049openalex-snapshot
Reducing Off-Chip Miss Penalty by Exploiting Underutilised On-Chip Router Buffers
inferred← citeshttps://doi.org/10.1109/iccd50377.2020.00050openalex-snapshot
Router Buffer Caching for Managing Shared Cache Blocks in Tiled Multi-Core Processors
inferred← citeshttps://doi.org/10.1109/icpads.2009.32openalex-snapshot
Snooping and Ordering Ring - An Efficient Cache Coherence Protocol for Ring Connected CMP
inferred← citeshttps://doi.org/10.1109/icpp.2011.34openalex-snapshot
PEPCP: A Power-Efficient Parallel Coherence Protocol for Large-Scale Network-on-Chip
inferred← citeshttps://doi.org/10.1109/icsp51882.2021.9408861openalex-snapshot
Microprocessor Architecture and Design in Post Exascale Computing Era
inferred← citeshttps://doi.org/10.1109/igcc.2015.7393679openalex-snapshot
Cross-Chip: Low power processor-to-memory nanophotonic interconnect architecture
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An interconnect-aware power efficient cache coherence protocol for CMPs
inferred← citeshttps://doi.org/10.1109/ipdpsw.2010.5470910openalex-snapshot
T-NUCA - a novel approach to non-uniform access latency cache architectures for 3D CMPs
inferred← citeshttps://doi.org/10.1109/ispa.2012.34openalex-snapshot
Bandwidth Adaptive Write-update Optimizations for Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/ispass69572.2026.00020openalex-snapshot
Characterization of Coherent Data Movement in Scaled-Out Shared Memory Systems
inferred← citeshttps://doi.org/10.1109/isvlsi49217.2020.00036openalex-snapshot
Exploiting On-Chip Routers to Store Dirty Cache Blocks in Tiled Chip Multi-processors
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Exploiting New Interconnect Technologies in On-Chip Communication
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BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP
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Transaction-Aware Network-on-Chip Resource Reservation
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Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow
inferred← citeshttps://doi.org/10.1109/micro.2007.33openalex-snapshot
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0
inferred← citeshttps://doi.org/10.1109/micro.2008.4771777openalex-snapshot
Virtual tree coherence: Leveraging regions and in-network multicast trees for scalable cache coherence
inferred← citeshttps://doi.org/10.1109/micro.2012.40openalex-snapshot
Predicting Coherence Communication by Tracking Synchronization Points at Run Time
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Research Challenges for On-Chip Interconnection Networks
inferred← citeshttps://doi.org/10.1109/nas.2010.25openalex-snapshot
Fast Hierarchical Cache Directory: A Scalable Cache Organization for Large-Scale CMP
inferred← citeshttps://doi.org/10.1109/nocs.2007.42openalex-snapshot
The Power of Priority: NoC Based Distributed Cache Coherency
inferred← citeshttps://doi.org/10.1109/nocs.2012.14openalex-snapshot
Heterogeneous NoC Design for Efficient Broadcast-based Coherence Protocol Support
inferred← citeshttps://doi.org/10.1109/pact.2009.24openalex-snapshot
DDCache: Decoupled and Delegable Cache Data and Metadata
inferred← citeshttps://doi.org/10.1109/pact.2011.11openalex-snapshot
POPS: Coherence Protocol Optimization for Both Private and Shared Data
inferred← citeshttps://doi.org/10.1109/pact52795.2021.00024openalex-snapshot
Invalidate or Update? Revisiting Coherence for Tomorrow's Cache Hierarchies
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An implementation of a directory protocol for a cache coherent system on FPGAs
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Workload adaptive shared memory multicore processors with reconfigurable interconnects
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Extending CC-NUMA systems to support write update optimizations
inferred← citeshttps://doi.org/10.1109/tc.2011.195openalex-snapshot
Subspace Snooping: Exploiting Temporal Sharing Stability for Snoop Reduction
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PDG_GEN: A Methodology for Fast and Accurate Simulation of On-Chip Networks
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Designing a Physical Locality Aware Coherence Protocol for Chip-Multiprocessors
inferred← citeshttps://doi.org/10.1109/tc.2013.217openalex-snapshot
Adaptive Cache Coherence Mechanisms with Producer–Consumer Sharing Optimization for Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/tc.2017.2773061openalex-snapshot
NUDA: Non-Uniform Directory Architecture for Scalable Chip Multiprocessors
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Opportunistic Caching in NoC: Exploring Ways to Reduce Miss Penalty
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An Open-Source Platform for High-Performance Non-Coherent On-Chip Communication
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Software-Defined Multimedia Streaming System Aided By Variable-Length Interval In-Network Caching
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Adaptive-Tree Multicast: Efficient Multidestination Support for CMP Communication Substrate
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AROMa: Aging-Aware Deadlock-Free Adaptive Routing Algorithm and Online Monitoring in 3D NoCs
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81.6 GOPS Object Recognition Processor Based on a Memory-Centric NoC
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FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow
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A Power Efficient Dual Link Mesh NoC Architecture to Support Nonuniform Traffic Arbitration at Routing Logic
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Hierarchical Cluster Based NoC Design Using Wireless Interconnects for Coherence Support
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Proximity-aware directory-based coherence for multi-core processor architectures
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A novel dimensionally-decomposed router for on-chip communication in 3D architectures
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A novel dimensionally-decomposed router for on-chip communication in 3D architectures
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A consistency architecture for hierarchical shared caches
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Comparison of memory write policies for NoC based multicore cache coherent systems
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Improving support for locality and fine-grain sharing in chip multiprocessors
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Leveraging on-chip networks for data cache migration in chip multiprocessors
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Push-assisted migration of real-time tasks in multi-core processors
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Push-assisted migration of real-time tasks in multi-core processors
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In-network coherence filtering
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An analysis of on-chip interconnection networks for large-scale chip multiprocessors
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Proximity coherence for chip multiprocessors
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An adaptive cache coherence protocol for chip multiprocessors
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Run-time energy management of manycore systems through reconfigurable interconnects
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A composite and scalable cache coherence protocol for large scale CMPs
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Inferring packet dependencies to improve trace based simulation of on-chip networks
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An optimized multicore cache coherence design for exploiting communication locality
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Towards network-on-chip agreement protocols
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Transient-Execution Attacks: A Computer Architect Perspective
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A Workload-Adaptive and Reconfigurable Bus Architecture for Multicore Processors
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Multi-Core Cache Hierarchies
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On-Chip Networks, Second Edition
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Shared Memory Networks On Chip Architecture
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Smart Memory and Network-On-Chip Design for High-Performance Shared-Memory Chip Multiprocessors
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Efficient techniques to provide scalability for token-based cache coherence protocols.
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Latency criticality aware on-chip communication
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Leveraging on-chip networks for efficient prediction on multicore coherence
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