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An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/4.962279openalex-snapshot
An embedded 32-b microprocessor core for low-power and high-performance applications
inferredcites →https://doi.org/10.1109/40.768496openalex-snapshot
Environment for PowerPC microarchitecture exploration
inferredcites →https://doi.org/10.1109/hpca.2002.995696openalex-snapshot
Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling
inferredcites →https://doi.org/10.1109/hpca.2005.10openalex-snapshot
Chip Multithreading: Opportunities and Challenges
inferredcites →https://doi.org/10.1109/hpca.2005.25openalex-snapshot
Performance, Energy, and Thermal Considerations for SMT and CMP Architectures
inferredcites →https://doi.org/10.1109/hpca.2006.1598109openalex-snapshot
CMP Design Space Exploration Subject to Physical Constraints
inferredcites →https://doi.org/10.1109/hpca.2006.1598114openalex-snapshot
Dynamic Power-Performance Adaptation of Parallel Computation on Chip Multiprocessors
inferredcites →https://doi.org/10.1109/iccd.2004.1347928openalex-snapshot
Best of both latency and throughput
inferredcites →https://doi.org/10.1109/isca.2004.1310764openalex-snapshot
Single-ISA heterogeneous multi-core architectures for multithreaded workload performance
inferredcites →https://doi.org/10.1109/isca.2005.36openalex-snapshot
Mitigating Amdahls Law through EPI Throttling
inferredcites →https://doi.org/10.1109/isca.2006.39openalex-snapshot
Techniques for Multicore Thermal Management: Classification and New Exploration
inferredcites →https://doi.org/10.1109/ispass.2001.990695openalex-snapshot
Balancing thoughput and fairness in SMT processors
inferredcites →https://doi.org/10.1109/ispass.2005.1430567openalex-snapshot
Power-Performance Implications of Thread-level Parallelism on Chip Multiprocessors
inferredcites →https://doi.org/10.1109/isscc.2005.1493990openalex-snapshot
Power and temperature control on a 90nm itanium~-family processor
inferredcites →https://doi.org/10.1109/jssc.2005.859902openalex-snapshot
Power and Temperature Control on a 90-nm Itanium Family Processor
inferredcites →https://doi.org/10.1109/mc.2003.1250883openalex-snapshot
Dynamically tuning processor resources with adaptive processing
inferredcites →https://doi.org/10.1109/micro.2001.991129openalex-snapshot
Handling long-latency loads in a simultaneous multithreading processor
inferredcites →https://doi.org/10.1109/micro.2003.1253185openalex-snapshot
Single-ISA heterogeneous multi-core architectures: the potential for processor power reduction
inferredcites →https://doi.org/10.1109/micro.2004.12openalex-snapshot
Conjoined-Core Chip Multiprocessing
inferredcites →https://doi.org/10.1109/mm.2004.1289290openalex-snapshot
IBM power5 chip: a dual-core multithreaded processor
inferredcites →https://doi.org/10.1109/mm.2005.34openalex-snapshot
Montecito: A Dual-Core, Dual-Thread Itanium Processor
inferredcites →https://doi.org/10.1109/pact.2005.42openalex-snapshot
Maximizing CMP throughput with mediocre cores
inferredcites →https://doi.org/10.1109/soc.2003.1241556openalex-snapshot
Dynamic power management for embedded systems [SOC design]
inferredcites →https://doi.org/10.1109/wwc.2004.1437388openalex-snapshot
Characterizing the impact of different memory-intensity levels
inferredcites →https://doi.org/10.1145/1024393.1024423openalex-snapshot
Formal online methods for voltage/frequency control in multiple clock domain microprocessors
inferredcites →https://doi.org/10.1145/1028176.1006707openalex-snapshot
Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance
inferredcites →https://doi.org/10.1145/1077603.1077637openalex-snapshot
Coordinated, distributed, formal energy management of chip multiprocessors
inferredcites →https://doi.org/10.1145/1080695.1069995openalex-snapshot
Mitigating Amdahl's Law through EPI Throttling
inferredcites →https://doi.org/10.1145/1150019.1136493openalex-snapshot
Techniques for Multicore Thermal Management
inferredcites →https://doi.org/10.1145/1217935.1217974openalex-snapshot
Balancing power consumption in multiprocessor systems
inferredcites →https://doi.org/10.1145/237090.237140openalex-snapshot
The case for a single-chip multiprocessor
inferredcites →https://doi.org/10.1145/605397.605403openalex-snapshot
Automatically characterizing large scale program behavior
inferredcites →https://doi.org/10.1145/859618.859621openalex-snapshot
Profile-based dynamic voltage and frequency scaling for a multiple clock domain microprocessor
inferredcites →https://doi.org/10.1145/859619.859621openalex-snapshot
Profile-based dynamic voltage and frequency scaling for a multiple clock domain microprocessor
inferredcites →https://doi.org/10.1145/871506.871561openalex-snapshot
Reducing power density through activity migration
inferredcites →https://doi.org/10.1147/rd.475.0653openalex-snapshot
New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessors
inferredcites →https://doi.org/10.2139/ssrn.4941535openalex-snapshot
Investigating the Effects of Task Scheduling on Thermal Behavior
inferredcites →https://doi.org/10.5445/ir/1000048145openalex-snapshot
Event-Driven Thermal Management in SMP Systems
inferredcites →https://doi.org/10.5555/563998.564038openalex-snapshot
Handling long-latency loads in a simultaneous multithreading processor
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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General-Purpose Multi-core Processors
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Design Space Exploration Supporting Run-Time Resource Management
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Design Space Exploration of Parallel Architectures
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Adaptability: The Key for Future Embedded Systems
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Energy-Efficient Design Techniques
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Background and Related Works
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Operation-Aware Power Capping
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NuPow: Managing Power on NUMA Multiprocessors with Domain-Level Voltage and Frequency Control
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Post-Silicon Customization Using Deep Neural Networks
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A Run-Time System for Power-Constrained HPC Applications
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Exploration of Load Balancing Thresholds to Save Energy on Iterative Applications
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Background and Related Work
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Scheduling for Better Energy Efficiency on Many-Core Chips
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Secure Power Management and Delivery Within Intelligent Power Networks on-Chip
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Communication Based Proactive Link Power Management
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Accomodating Diversity in CMPs with Heterogeneous Frequencies
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Token3D: Reducing Temperature in 3D Die-Stacked CMPs through Cycle-Level Power Control Mechanisms
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Reducing Energy Usage with Memory and Computation-Aware Dynamic Frequency Scaling
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Communication Based Proactive Link Power Management
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Thermal-Aware Task Assignment for Real-Time Applications on Multi-Core Systems
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3-D ICs for Low Power/Energy
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Analysis of Power Management Techniques in Multicore Processors
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Power Modeling at High-Performance Computing Processors
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An Innovative Power-Gating Technique for Leakage and Ground Bounce Control in System-on-a-Chip (SOC)
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Efficient inter-core power and thermal balancing for multicore processors
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Dynamic workload-aware DVFS for multicore systems using machine learning
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Feasibility analysis of baseband architectures for multi-GNSS receivers
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Empirical and analytical approaches for web server power modeling
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A novel energy-efficient scheduling model for multi-core systems
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The fast evolving landscape of on-chip communication
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Efficient Worst-Case Temperature Evaluation for Thermal-Aware Assignment of Real-Time Applications on MPSoCs
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Toward on-chip datacenters: a perspective on general trends and on-chip particulars
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Managing power constraints in a single-core scenario through power tokens
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Adaptive global power optimization for Web servers
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Evaluation of Low-Power Computing when Operating on Subsets of Multicore Processors
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Energy Efficient Block-Partitioned Multicore Processors for Parallel Applications
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CPicker: Leveraging Performance-Equivalent Configurations to Improve Data Center Energy Efficiency
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Task Deadline-Aware Energy-Efficient Scheduling Model for a Virtualized Cloud
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Deadline Aware Energy-Efficient Task Scheduling Model for a Virtualized Server
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AI enhanced energy governance for solar powered data centers toward intelligent sustainable and resilient architectures
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Techniques to Measure, Model, and Manage Power
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Accurately modeling GPGPU frequency scaling with the CRISP performance model
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Dynamic Power Management for Dark Silicon Multicore Processors ☆ ☆Parts of this chapter describe the author's prior work in publications [1–3]. Consequently, some of the text and the figures in this chapter are adapted from these prior publications.
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Shared resource aware scheduling on power-constrained tiled many-core processors
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Sub-threshold synchronizer
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Power and thermal constraints of modern system-on-a-chip computer
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Parallel job scheduling for power constrained HPC systems
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A Mathematical Method for Online Autotuning of Power and Energy Consumption with Corrected Temperature Effects
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Using Power Demand and Residual Load Imbalance in the Load Balancing to Save Energy of Parallel Systems
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Energy-performance trade-off analysis of parallel algorithms for shared memory architectures
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Data center power and performance optimization through global selection of P-states and utilization rates
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Understanding hardware and software metrics with respect to power consumption
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Optimality of dynamic voltage/frequency scaling in many-core systems with voltage-frequency islands
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Counter-Based Power Modeling Methods: Top-Down vs. Bottom-Up
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Big Data promises value: is hardware technology taken onboard?
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Power Delivery Networks for Embedded Mobile SoCs: Architectural Advancements and Design Challenges
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Learning-based power management for multi-core processors via idle period manipulation
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Estimation based power and supply voltage management for future RF-powered multi-core smart cards
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Optimizing job performance under a given power constraint in HPC centers
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Portable, scalable, per-core power estimation for intelligent resource management
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Energy-efficient synchronization through program patterns
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Improving Provisioned Power Efficiency in HPC Systems with GPU-CAPP
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Variation-aware dynamic voltage/frequency scaling
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Scalably verifiable dynamic power management
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Dynamic management of TurboMode in modern multi-core chips
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XChange: A market-based approach to scalable dynamic multi-resource allocation in multicore architectures
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Adrenaline: Pinpointing and reining in tail queries with quick voltage boosting
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Improving smartphone user experience by balancing performance and energy with probabilistic QoS guarantee
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Application-Specific Performance-Aware Energy Optimization on Android Mobile Devices
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Adaptive Voltage/Frequency Scaling and Core Allocation for Balanced Energy and Performance on Multicore CPUs
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Understanding the Impact of Socket Density in Density Optimized Servers
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Precise Runahead Execution
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Chasing Carbon: The Elusive Environmental Footprint of Computing
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ReTail: Opting for Learning Simplicity to Enable QoS-Aware Power Management in the Cloud
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DarkGates: A Hybrid Power-Gating Architecture to Mitigate the Performance Impact of Dark-Silicon in High Performance Processors
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Optimal Energy-Aware Scheduling in VFI-enabled Multicore Systems
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Linear programming based parallel job scheduling for power constrained systems
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Coordinated Optimization of the Performance of Processors and Memory in a Heterogeneous System under Energy Constraints
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Task Migration Algorithm to Reduce Temperature Imbalance Amongst Cores in Linux Based Multi-Core Processor Systems
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Value Based Scheduling for Oversubscribed Power-Constrained Homogeneous HPC Systems
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Efficient online computation of core speeds to maximize the throughput of thermally constrained multi-core processors
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Identifying the optimal energy-efficient operating points of parallel workloads
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Agent-based distributed power management for Kilo-core processors: Special Session: “Keeping Kilo-core chips cool: New directions and emerging solutions”
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TEI-Turbo: temperature effect inversion-aware turbo boost for finfet-based multi-core systems
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Supply and Demand Coordination in Energy Adaptive Computing
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Microarchitecture aware gate sizing: A framework for circuit-architecture co-optimization
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DPPC: Dynamic power partitioning and capping in chip multiprocessors
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Robust optimization of a Chip Multiprocessor's performance under power and thermal constraints
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Dynamic thread mapping for high-performance, power-efficient heterogeneous many-core systems
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Power capping of CPU-GPU heterogeneous systems through coordinating DVFS and task mapping
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Comparison of single-ISA heterogeneous versus wide dynamic range processors for mobile applications
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Power-agility metrics: Measuring dynamic characteristics of energy proportionality
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Using Application-Level Thread Progress Information to Manage Power and Performance
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A review of energy efficiency technology in computer servers and cluster systems
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Data Center Sprinting: Enabling Computational Sprinting at the Data Center Level
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A novel approach to memory power estimation using machine learning
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Dynamic energy allocation for coordinated optimization in enterprise workloads
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Thermal analysis experiences of a tri-core SoC system
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Voltage and frequency island optimizations for many-core/networks-on-chip designs
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Hierarchical agent based NoC with dynamic online services
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Multi-core processors: A new way forward and challenges
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Heterogeneity-Aware Peak Power Management for Accelerator-Based Systems
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Analysis of Parallel Algorithms for Energy Conservation in Scalable Multicore Architectures
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Achieving Fair or Differentiated Cache Sharing in Power-Constrained Chip Multiprocessors
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On the Energy Complexity of Parallel Algorithms
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Adaptive Configuration Selection for Power-Constrained Heterogeneous Systems
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Evaluating Latency-Sensitive Applications: Performance Degradation in Datacenters with Restricted Power Budget
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The Case for Cross-Component Power Coordination on Power Bounded Systems
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Performance Maximization via Frequency Oscillation on Temperature Constrained Multi-core Processors
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On Performance and Energy Management in High Performance Computing Systems
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Green Streams for data-intensive software
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Green governors: A framework for Continuously Adaptive DVFS
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Fine-grained per-core frequency scheduling for power efficient-multicore execution
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An energy-constrained makespan optimization framework in fine-to coarse-grain partitioned multicore systems
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Fine-Grained Energy Efficiency Using Per-Core DVFS with an Adaptive Runtime System
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Application-Aware Power Management
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Energy-Performance Trade-offs on Energy-Constrained Devices with Multi-component DVFS
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Big or Little: A Study of Mobile Interactive Applications on an Asymmetric Multi-core Platform
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Optimizing Throughput and Latency under Given Power Budget for Network Packet Processing
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Energy efficient real-time task scheduling on CPU-GPU hybrid clusters
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Towards energy efficient scaling of scientific codes
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Autonomic power and performance management of high-performance servers
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Efficient microarchitecture policies for accurately adapting to power constraints
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Power and Performance Management in Priority-Type Cluster Computing Systems
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Willow: A Control System for Energy and Thermal Adaptive Computing
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A Novel Power Management for CMP Systems in Data-Intensive Environment
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Power Token Balancing: Adapting CMPs to Power Constraints for Parallel Multithreaded Workloads
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Energy-Efficient Scheduling for Best-Effort Interactive Services to Achieve High Response Quality
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Power and Performance Characterization and Modeling of GPU-Accelerated Systems
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PowerFCT: Power Optimization of Data Center Network with Flow Completion Time Constraints
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SprintCon: Controllable and Efficient Computational Sprinting for Data Center Servers
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Beyond DVFS: A First Look at Performance under a Hardware-Enforced Power Bound
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Performance Benefits of Heterogeneous Computing in HPC Workloads
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PowerTune: Differentiated Power Allocation in Over-Provisioned Multicore Systems
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