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Conjoined-Core Chip Multiprocessing
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/ipdps.2004.1303010openalex-snapshot
Clustered multithreaded architectures -pursuing both IPC and cycle time
inferredcites →https://doi.org/10.1109/ipps.1998.669992openalex-snapshot
A clustered approach to multithreaded processors
inferredcites →https://doi.org/10.1109/isca.1995.524578openalex-snapshot
Simultaneous multithreading: Maximizing on-chip parallelism
inferredcites →https://doi.org/10.1109/isca.2000.854398openalex-snapshot
Piranha: a scalable architecture based on single-chip multiprocessing
inferredcites →https://doi.org/10.1109/micro.2003.1253185openalex-snapshot
Single-ISA heterogeneous multi-core architectures: the potential for processor power reduction
inferredcites →https://doi.org/10.1109/mm.2003.1261391openalex-snapshot
Discovering and exploiting program phases
inferredcites →https://doi.org/10.1109/pact.2001.953301openalex-snapshot
Area and system clock effects on SMT/CMP processors
inferredcites →https://doi.org/10.1145/356989.357011openalex-snapshot
Symbiotic jobscheduling for a simultaneous mutlithreading processor
inferredcites →https://doi.org/10.1145/378239.379047openalex-snapshot
On-chip communication architecture for OC-768 network processors
inferredcites →https://doi.org/10.1145/378993.379244openalex-snapshot
Symbiotic jobscheduling for a simultaneous multithreaded processor
inferredcites →https://doi.org/10.5555/645988.674171openalex-snapshot
Area and System Clock Effects on SMT/CMP Processors
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/11942634_9openalex-snapshot
L2-Cache Hierarchical Organizations for Multi-core Architectures
inferred← citeshttps://doi.org/10.1007/978-1-4419-0263-4_7openalex-snapshot
Throughput-Oriented Multicore Processors
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Rapid Technology-Aware Design Space Exploration for Embedded Heterogeneous Multiprocessors
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An Evaluation of OpenMP on Current and Emerging Multithreaded/Multicore Processors
inferred← citeshttps://doi.org/10.1007/978-3-540-77560-7_24openalex-snapshot
Compiler Techniques for Reducing Data Cache Miss Rate on a Multithreaded Architecture
inferred← citeshttps://doi.org/10.1007/978-3-642-13119-6_12openalex-snapshot
Function Units Sharing between Neighbor Cores in CMP
inferred← citeshttps://doi.org/10.1007/978-3-642-19448-1_3openalex-snapshot
Data Layout for Cache Performance on a Multithreaded Architecture
inferred← citeshttps://doi.org/10.1007/s10766-006-0017-yopenalex-snapshot
Supporting Microthread Scheduling and Synchronisation in CMPs
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Theoretical peak FLOPS per instruction set: a tutorial
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DITVA: Dynamic Inter-Thread Vectorization Architecture
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On the performance benefits of sharing and privatizing second and third-level cache memories in homogeneous multi-core architectures
inferred← citeshttps://doi.org/10.1016/s0065-2458(06)69001-3openalex-snapshot
The Architecture of Efficient Multi-Core Processors: A Holistic Approach
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A HW/SW co-designed heterogeneous multi-core virtual machine for energy-efficient general purpose computing
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Enabling dynamic heterogeneity through core-on-core stacking
inferred← citeshttps://doi.org/10.1109/dac18072.2020.9218614openalex-snapshot
Enhancing Thread-Level Parallelism in Asymmetric Multicores using Transparent Instruction Offloading
inferred← citeshttps://doi.org/10.1109/dsd.2011.98openalex-snapshot
Phase-Guided Scheduling on Single-ISA Heterogeneous Multicore Processors
inferred← citeshttps://doi.org/10.1109/dsn.2010.5544915openalex-snapshot
StageWeb: Interweaving pipeline stages into a wearout and variation tolerant CMP fabric
inferred← citeshttps://doi.org/10.1109/fpt.2011.6132724openalex-snapshot
Sharing FPUs in many-soft-cores
inferred← citeshttps://doi.org/10.1109/green.2012.6200965openalex-snapshot
Energy-Efficient Phase-Aware Scheduling for Heterogeneous Multicore Processors
inferred← citeshttps://doi.org/10.1109/hpca.2012.6169037openalex-snapshot
Dynamically heterogeneous cores through 3D resource pooling
inferred← citeshttps://doi.org/10.1109/hpca.2013.6522339openalex-snapshot
Illusionist: Transforming lightweight cores into aggressive cores on demand
inferred← citeshttps://doi.org/10.1109/hpca.2019.00037openalex-snapshot
Enhancing Server Efficiency in the Face of Killer Microseconds
inferred← citeshttps://doi.org/10.1109/hpcc64274.2024.00047openalex-snapshot
HIDC: Heterogeneous-ISA Dynamic Core
inferred← citeshttps://doi.org/10.1109/iccad.2006.320015openalex-snapshot
Conjoining Soft-Core FPGA Processors
inferred← citeshttps://doi.org/10.1109/iccd.2010.5647566openalex-snapshot
A study on performance benefits of core morphing in an asymmetric multicore processor
inferred← citeshttps://doi.org/10.1109/iccd.2014.6974710openalex-snapshot
The heterogeneous block architecture
inferred← citeshttps://doi.org/10.1109/icpp.2009.48openalex-snapshot
Thread Merging Schemes for Multithreaded Clustered VLIW Processors
inferred← citeshttps://doi.org/10.1109/icpp.2010.35openalex-snapshot
Hyperscalar: A Novel Dynamically Reconfigurable Multi-core Architecture
inferred← citeshttps://doi.org/10.1109/ipdps.2006.1639326openalex-snapshot
Coterminous locality and coterminous group data prefetching on chip-multiprocessors
inferred← citeshttps://doi.org/10.1109/ipdps.2006.1639598openalex-snapshot
Online strategies for high-performance power-aware thread execution on emerging multiprocessors
inferred← citeshttps://doi.org/10.1109/isca.2012.6237005openalex-snapshot
Simultaneous branch and warp interweaving for sustained GPU performance
inferred← citeshttps://doi.org/10.1109/ises58672.2023.00013openalex-snapshot
A Neural Network-Based Approach to Dynamic Core Morphing for AMPs
inferred← citeshttps://doi.org/10.1109/ispass.2017.7975265openalex-snapshot
Sharing the instruction cache among lean cores on an asymmetric CMP for HPC applications
inferred← citeshttps://doi.org/10.1109/ispdc.2008.63openalex-snapshot
Holistic Design of Multiple-Core Architectures
inferred← citeshttps://doi.org/10.1109/isvlsi.2013.6654621openalex-snapshot
A study on polymorphing superscalar processor dynamically to improve power efficiency
inferred← citeshttps://doi.org/10.1109/lca.2018.2889042openalex-snapshot
Improving GPU Multitasking Efficiency Using Dynamic Resource Sharing
inferred← citeshttps://doi.org/10.1109/mc.2005.379openalex-snapshot
Heterogeneous chip multiprocessors
inferred← citeshttps://doi.org/10.1109/micro.2006.8openalex-snapshot
An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget
inferred← citeshttps://doi.org/10.1109/micro.2007.41openalex-snapshot
Composable Lightweight Processors
inferred← citeshttps://doi.org/10.1109/micro.2007.9openalex-snapshot
The Art of Deception: Adaptive Precision Reduction for Area Efficient Physics Acceleration
inferred← citeshttps://doi.org/10.1109/micro.2010.30openalex-snapshot
Erasing Core Boundaries for Robust and Configurable Performance
inferred← citeshttps://doi.org/10.1109/micro.2012.37openalex-snapshot
Composite Cores: Pushing Heterogeneity Into a Core
inferred← citeshttps://doi.org/10.1109/micro56248.2022.00025openalex-snapshot
big.VLITTLE: On-Demand Data-Parallel Acceleration for Mobile Systems on Chip
inferred← citeshttps://doi.org/10.1109/pact.2009.44openalex-snapshot
Core-Selectability in Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/pact.2011.18openalex-snapshot
Performance Per Watt Benefits of Dynamic Core Morphing in Asymmetric Multicores
inferred← citeshttps://doi.org/10.1109/qest.2005.16openalex-snapshot
Integrating multiple forms of multithreaded execution on multi-SMT systems: a study with scientific applications
inferred← citeshttps://doi.org/10.1109/sasp.2010.5521138openalex-snapshot
Design of a custom VEE core in a chip multiprocessor
inferred← citeshttps://doi.org/10.1109/sbac-pad.2006.5openalex-snapshot
32-core CMP with multi-sliced L2: 2 and 4 cores sharing a L2 slice
inferred← citeshttps://doi.org/10.1109/tc.2015.2419669openalex-snapshot
Exploring Fine-Grained Heterogeneity with Composite Cores
inferred← citeshttps://doi.org/10.1109/tpds.2011.214openalex-snapshot
High-Performance Energy-Efficient Multicore Embedded Computing
inferred← citeshttps://doi.org/10.1109/ubmk.2019.8907005openalex-snapshot
iMODE (interactive MOod Detection Engine) Processor
inferred← citeshttps://doi.org/10.1109/vlsid.2014.42openalex-snapshot
Performance and Power Benefits of Sharing Execution Units between a High Performance Core and a Low Power Core
inferred← citeshttps://doi.org/10.1145/1105734.1105744openalex-snapshot
Dynamically configurable shared CMP helper engines for improved performance
inferred← citeshttps://doi.org/10.1145/1128022.1128029openalex-snapshot
Dynamic thread assignment on heterogeneous multiprocessor architectures
inferred← citeshttps://doi.org/10.1145/1176760.1176802openalex-snapshot
Improving the performance and power efficiency of shared helpers in CMPs
inferred← citeshttps://doi.org/10.1145/1188455.1188537openalex-snapshot
Architecture---The potential energy efficiency of vector acceleration
inferred← citeshttps://doi.org/10.1145/1242531.1242567openalex-snapshot
Performance/area efficiency in chip multiprocessors with micro-caches
inferred← citeshttps://doi.org/10.1145/1346281.1346298openalex-snapshot
Accurate branch prediction for short threads
inferred← citeshttps://doi.org/10.1145/1353534.1346298openalex-snapshot
Accurate branch prediction for short threads
inferred← citeshttps://doi.org/10.1145/1353535.1346298openalex-snapshot
Accurate branch prediction for short threads
inferred← citeshttps://doi.org/10.1145/1353536.1346298openalex-snapshot
Accurate branch prediction for short threads
inferred← citeshttps://doi.org/10.1145/1463768.1463770openalex-snapshot
Dynamic power management framework for multi-core portable embedded system
inferred← citeshttps://doi.org/10.1145/1629395.1629403openalex-snapshot
Hybrid multithreading for VLIW processors
inferred← citeshttps://doi.org/10.1145/1854273.1854284openalex-snapshot
Dynamically managed multithreaded reconfigurable architectures for chip multiprocessors
inferred← citeshttps://doi.org/10.1145/2024724.2024910openalex-snapshot
Shared reconfigurable fabric for multi-core customization
inferred← citeshttps://doi.org/10.1145/2366231.2337166openalex-snapshot
Simultaneous branch and warp interweaving for sustained GPU performance
inferred← citeshttps://doi.org/10.1145/2445572.2445577openalex-snapshot
The McPAT Framework for Multicore and Manycore Architectures
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Low-latency adaptive mode transitions and hierarchical power management in asymmetric clustered cores
inferred← citeshttps://doi.org/10.1145/2593069.2596674openalex-snapshot
Enabling Dynamic Heterogeneity Through Core-on-Core Stacking
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Does the Sharing of Execution Units Improve Performance/Power of Multicores?
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A Survey of Techniques for Architecting and Managing Asymmetric Multicore Processors
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Entropy: algoritmo de substituição de linhas de cache inspirado na entropia da informação.
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Area-efficient floorplans and interconnects for homogeneous multi-core architectures
inferred← citeshttps://doi.org/10.2197/ipsjtsldm.8.51openalex-snapshot
Heterogeneous Multi-core Architectures
inferred← citeshttps://doi.org/10.2200/s00458ed1v01y201212cac021openalex-snapshot
Multithreading Architecture
inferred← citeshttps://doi.org/10.5555/1331699.1331707openalex-snapshot
Optimal versus Heuristic Global Code Scheduling
inferred← citeshttps://doi.org/10.5555/1331699.1331733openalex-snapshot
Composable Lightweight Processors
inferred← citeshttps://doi.org/10.5555/1898699.1898824openalex-snapshot
Online strategies for high-performance power-aware thread execution on emerging multiprocessors
inferred← citeshttps://doi.org/10.5555/2190025.2190070openalex-snapshot
A HW/SW co-designed heterogeneous multi-core virtual machine for energy-efficient general purpose computing
inferred← citeshttps://doi.org/10.5821/dissertation-2117-114621openalex-snapshot
Multicore architecture optimizations for HPC applications
inferred← citeshttps://doi.org/10.5821/dissertation-2117-95043openalex-snapshot
Design of a distributed memory unit for clustered microarchitectures
inferred← citeshttps://doi.org/10.5821/dissertation-2117-95098openalex-snapshot
Improving multithreading performance for clustered VLIW architectures.
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Specialization and reconfiguration of lightweight mobile processors for data-parallel applications
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Transformer le TLP en DLP avec l'architecture de vectorisation dynamique inter-thread
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Online Management of Resilient and Power Efficient Multicore Processors
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Datacenter Architectures for the Microservices Era
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