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Revisiting the Sequential Programming Model for Multi-Core
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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Restructuring programs for high-speed computers with Polaris
inferredcites →https://doi.org/10.1109/isca.1998.694778openalex-snapshot
Threaded multiple path execution
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From Sequential Programs to Concurrent Threads
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Exceeding the dataflow limit via value prediction
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A dynamic multithreading processor
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Automatic Thread Extraction with Decoupled Software Pipelining
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A Practical Approach to Exploiting Coarse-Grained Pipeline Parallelism in C Programs
inferredcites →https://doi.org/10.1109/pact.2003.1238002openalex-snapshot
Y-branches: when you come to a fork in the road, take it
inferredcites →https://doi.org/10.1109/pact.2004.1342552openalex-snapshot
Decoupled software pipelining with the synchronization array
inferredcites →https://doi.org/10.1109/pact.2007.4336199openalex-snapshot
Speculative Decoupled Software Pipelining
inferredcites →https://doi.org/10.1109/superc.1992.236682openalex-snapshot
Compiler code transformations for superscalar-based high-performance systems
inferredcites →https://doi.org/10.1145/1065944.1065964openalex-snapshot
Exposing speculative thread parallelism in SPEC2000
inferredcites →https://doi.org/10.1145/1082469.1082471openalex-snapshot
The STAMPede approach to thread-level speculation
inferredcites →https://doi.org/10.1145/1089008.1089010openalex-snapshot
Tradeoffs in buffering speculative memory state for thread-level speculation in multiprocessors
inferredcites →https://doi.org/10.1145/1133981.1133983openalex-snapshot
The Atomos transactional programming language
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A framework for unrestricted whole-program optimization
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A probabilistic pointer analysis for speculative optimizations
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What do high-level memory models mean for transactions?
inferredcites →https://doi.org/10.1145/1250734.1250760openalex-snapshot
Software behavior oriented parallelization
inferredcites →https://doi.org/10.1145/207110.207117openalex-snapshot
Accurate static branch prediction by value range propagation
inferredcites →https://doi.org/10.1145/263699.263719openalex-snapshot
Maximizing parallelism and minimizing synchronization with affine transforms
inferredcites →https://doi.org/10.1145/277650.277725openalex-snapshot
The implementation of the Cilk-5 multithreaded language
inferredcites →https://doi.org/10.1145/349299.349311openalex-snapshot
Modular interprocedural pointer analysis using access paths
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A stream compiler for communication-exposed architectures
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Extracting Coarse-Grained Pipelined Parallelism Out of Sequential Applications for Parallel Processor Arrays
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Concurrent Separation Logic for Pipelined Parallelization
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Speculative Parallelization of Sequential Loops on Multicores
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Manual Parallelization Versus State-of-the-Art Parallelization Techniques
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DOcyclical: A Latency-Resistant Cyclic Multi-Threading Approach for Automatic Program Parallelization
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Alchemist: A Transparent Dependence Distance Profiling Infrastructure
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Loop Parallelization using Dynamic Commutativity Analysis
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Cache-based cross-iteration coherence for speculative parallelization
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Context-Aware Memory Profiling for Speculative Parallelism
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Dynamic parallelization of JavaScript applications using an ultra-lightweight speculation mechanism
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Con?ict-Avoidance in Multicore Caching for Data-Similar Executions
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Implementation of Longest Common Subsequence Algorithm Using Thread Parallelization in Java
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Cooperative parallelization
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Speculative memory: An architectural support for explicit speculations in multithreaded programming
inferred← citeshttps://doi.org/10.1109/icppw.2009.25openalex-snapshot
Supporting Multitasking of Pipelined Computations on Embedded Parallel Processor Arrays
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Critical-Path-Guided Interactive Parallelisation
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Understanding parallelism-inhibiting dependences in sequential Java programs
inferred← citeshttps://doi.org/10.1109/isca.2014.6853215openalex-snapshot
HELIX-RC: An architecture-compiler co-design for automatic parallelization of irregular programs
inferred← citeshttps://doi.org/10.1109/isca45697.2020.00024openalex-snapshot
T4: Compiling Sequential Code for Effective Speculative Parallelization in Hardware
inferred← citeshttps://doi.org/10.1109/iwmse.2009.5071384openalex-snapshot
SPARTAN: A software tool for Parallelization Bottleneck Analysis
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Parallel assertions for debugging parallel programs
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A Practical Approach to Exploiting Coarse-Grained Pipeline Parallelism in C Programs
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Copy or Discard execution model for speculative parallelization on multicores
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Scalable Speculative Parallelization on Commodity Clusters
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Revisiting the Sequential Programming Model for the Multicore Era
inferred← citeshttps://doi.org/10.1109/mm.2010.52openalex-snapshot
Future Directions in Computer Architecture Research
inferred← citeshttps://doi.org/10.1109/mm.2010.54openalex-snapshot
Programming Multicores: Do Applications Programmers Need to Write Explicitly Parallel Programs?
inferred← citeshttps://doi.org/10.1109/tpds.2009.47openalex-snapshot
Performance Evaluation of Dynamic Speculative Multithreading with the Cascadia Architecture
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PROMPT: A Fast and Extensible Memory Profiling Framework
inferred← citeshttps://doi.org/10.18260/1-2--4739openalex-snapshot
Educational Goals For Embedded Systems In The Multicore Era
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Transactional Memory, 2nd edition
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Automatic Parallelization: An Overview of Fundamental Compiler Techniques
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Defining, Understanding, and Addressing Big Data
inferred← citeshttps://doi.org/10.4028/www.scientific.net/amm.58-60.298openalex-snapshot
Study on the Mapping of Streaming Application on Many-Core Architecture
inferred← citeshttps://doi.org/10.47749/t/unicamp.2012.877881openalex-snapshot
Mecanismo para execução especulativa de aplicações paralelizadas por técnicas DOPIPE usando replicação de estágios
inferred← citeshttps://doi.org/10.5821/dissertation-2117-94989openalex-snapshot
Towards lightweight and high-performance hardware transactional memory
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Using statistical methods to model and estimate the time variability of programs executed on multicore architectures
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