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A Practical Approach to Exploiting Coarse-Grained Pipeline Parallelism in C Programs
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Outgoing claims: the papers this work cites, builds on, or argues with.
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Dynamic Memory Design for Low Data-Retention Power
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StreamIt: A Language for Streaming Applications
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Overcoming the limitations of the traditional loop parallelization
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Run-time parallelization: Its time has come
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Data and Computation Transformations for Brook Streaming Applications on Multiprocessors
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Retention-Aware Placement in DRAM (RAPID): Software Methods for Quasi-Non-Volatile DRAM
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3D processing technology and its impact on iA32 microprocessors
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BioBench: A Benchmark Suite of Bioinformatics Applications
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A Case for Compressing Traces with BDDs
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Programmable stream processors
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Automatic Thread Extraction with Decoupled Software Pipelining
inferredcites →https://doi.org/10.1109/micro.2006.18openalex-snapshot
Die Stacking (3D) Microarchitecture
inferredcites →https://doi.org/10.1109/micro.2007.20openalex-snapshot
Revisiting the Sequential Programming Model for Multi-Core
inferredcites →https://doi.org/10.1109/pact.2004.1342552openalex-snapshot
Decoupled software pipelining with the synchronization array
inferredcites →https://doi.org/10.1109/pact.2007.4336199openalex-snapshot
Speculative Decoupled Software Pipelining
inferredcites →https://doi.org/10.1109/tc.1980.1675676openalex-snapshot
High-Speed Multiprocessors and Compilation Techniques
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Compiler Support for Exploiting Coarse-Grained Pipelined Parallelism
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Automatically partitioning packet processing applications for pipelined architectures
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Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
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Compiling for stream processing
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Exploiting coarse-grained task, data, and pipeline parallelism in stream programs
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Function level parallelism driven by data dependencies
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Optimizing the DRAM refresh count for merged DRAM/logic LSIs
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Package Technology to Address the Memory Bandwidth Challenge for Terascale Computing
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Preliminary Design Review: GMTI Narrowband for the Basic PCA Integrated Radar-Tracker Application
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Incoming claims: where this work appears in other papers’ reference lists and arguments.
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A Low Power Real-time On-Chip Power Sensor in 45-nm SOI
inferred← citeshttps://doi.org/10.1109/test.2017.8242065openalex-snapshot
Cross-layer refresh mitigation for efficient and reliable DRAM systems: A comparative study
inferred← citeshttps://doi.org/10.1109/tii.2011.2166769openalex-snapshot
Expressing Coarse-Grain Dependencies Among Tasks in Shared Memory Programs
inferred← citeshttps://doi.org/10.1109/tmm.2011.2177079openalex-snapshot
Reducing DRAM Image Data Access Energy Consumption in Video Processing
inferred← citeshttps://doi.org/10.1109/tpds.2015.2461155openalex-snapshot
A Survey Of Techniques for Architecting DRAM Caches
inferred← citeshttps://doi.org/10.1109/tpds.2017.2763141openalex-snapshot
Alleviating Memory Refresh Overhead via Data Compression for High Performance and Energy Efficiency
inferred← citeshttps://doi.org/10.1109/tvlsi.2011.2165974openalex-snapshot
Optimizing Video Application Design for Phase-Change RAM-Based Main Memory
inferred← citeshttps://doi.org/10.1109/tvlsi.2014.2311798openalex-snapshot
Runtime Thermal Management for 3-D Chip-Multiprocessors With Hybrid SRAM/MRAM L2 Cache
inferred← citeshttps://doi.org/10.1109/vlsi-soc.2014.7004159openalex-snapshot
Optimized active and power-down mode refresh control in 3D-DRAMs
inferred← citeshttps://doi.org/10.1109/vlsid.2016.13openalex-snapshot
Massed Refresh: An Energy-Efficient Technique to Reduce Refresh Overhead in Hybrid Memory Cube Architectures
inferred← citeshttps://doi.org/10.1109/vts.2013.6548927openalex-snapshot
A hybrid ECC and redundancy technique for reducing refresh power of DRAMs
inferred← citeshttps://doi.org/10.1145/1394608.1382159openalex-snapshot
3D-Stacked Memory Architectures for Multi-core Processors
inferred← citeshttps://doi.org/10.1145/1394608.1382172openalex-snapshot
Self-Optimizing Memory Controllers
inferred← citeshttps://doi.org/10.1145/1654059.1654102openalex-snapshot
Future scaling of processor-memory interfaces
inferred← citeshttps://doi.org/10.1145/1669112.1669139openalex-snapshot
Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policy
inferred← citeshttps://doi.org/10.1145/1815961.1815973openalex-snapshot
Reducing cache power with low-cost, multi-bit error-correcting codes
inferred← citeshttps://doi.org/10.1145/1816038.1815973openalex-snapshot
Reducing cache power with low-cost, multi-bit error-correcting codes
inferred← citeshttps://doi.org/10.1145/1840845.1840930openalex-snapshot
Rank-aware cache replacement and write buffering to improve DRAM energy efficiency
inferred← citeshttps://doi.org/10.1145/1880037.1880040openalex-snapshot
Design exploration of hybrid caches with disparate memory technologies
inferred← citeshttps://doi.org/10.1145/1941553.1941580openalex-snapshot
Enhanced speculative parallelization via incremental recovery
inferred← citeshttps://doi.org/10.1145/2024724.2024738openalex-snapshot
Power management of hybrid DRAM/PRAM-based main memory
inferred← citeshttps://doi.org/10.1145/2133382.2133386openalex-snapshot
Improving System Energy Efficiency with Memory Rank Subsetting
inferred← citeshttps://doi.org/10.1145/2155620.2155673openalex-snapshot
Efficiently enabling conventional block sizes for very large die-stacked DRAM caches
inferred← citeshttps://doi.org/10.1145/2228360.2228477openalex-snapshot
Optimizing energy efficiency of 3-D multicore systems with stacked DRAM under power and thermal constraints
inferred← citeshttps://doi.org/10.1145/2432516.2432521openalex-snapshot
TLM modelling of 3D stacked wide I/O DRAM subsystems
inferred← citeshttps://doi.org/10.1145/2464996.2465002openalex-snapshot
Conservative row activation to improve memory power efficiency
inferred← citeshttps://doi.org/10.1145/2485922.2485927openalex-snapshot
Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems
inferred← citeshttps://doi.org/10.1145/2485922.2485957openalex-snapshot
Die-stacked DRAM caches for servers
inferred← citeshttps://doi.org/10.1145/2503210.2503215openalex-snapshot
Exploring DRAM organizations for energy-efficient and resilient exascale memories
inferred← citeshttps://doi.org/10.1145/2508148.2485927openalex-snapshot
Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems
inferred← citeshttps://doi.org/10.1145/2508148.2485957openalex-snapshot
Die-stacked DRAM caches for servers
inferred← citeshttps://doi.org/10.1145/2534393openalex-snapshot
Low-energy volatile STT-RAM cache design using cache-coherence-enabled adaptive refresh
inferred← citeshttps://doi.org/10.1145/2579669openalex-snapshot
Refresh pausing in DRAM memory systems
inferred← citeshttps://doi.org/10.1145/2600212.2600216openalex-snapshot
Improving energy efficiency of embedded DRAM caches for high-end computing systems
inferred← citeshttps://doi.org/10.1145/2627369.2627626openalex-snapshot
eDRAM-based tiered-reliability memory with applications to low-power frame buffers
inferred← citeshttps://doi.org/10.1145/2818950.2818963openalex-snapshot
Achieving Yield, Density and Performance Effective DRAM at Extreme Technology Sizes
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