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Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-3-540-30102-8_3openalex-snapshot
Efficient Victim Mechanism on Sector Cache Organization
inferredcites →https://doi.org/10.1109/isca.1994.288133openalex-snapshot
Decoupled sectored caches: conciliating low tag implementation cost and low miss ratio
inferredcites →https://doi.org/10.1109/ispass.2005.1430562openalex-snapshot
Enhancing Multiprocessor Architecture Simulation Speed Using Matched-Pair Comparison
inferredcites →https://doi.org/10.1109/mm.2003.1196114openalex-snapshot
Itanium 2 processor microarchitecture
inferredcites →https://doi.org/10.1145/1080695.1069989openalex-snapshot
Temporal Streaming of Shared Memory
inferredcites →https://doi.org/10.1145/1080695.1069991openalex-snapshot
Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking
inferredcites →https://doi.org/10.1145/305138.305156openalex-snapshot
The pool of subsectors cache design
inferredcites →https://doi.org/10.1145/566408.566471openalex-snapshot
TLB and snoop energy-reduction using virtual caches in low-power chip-multiprocessors
inferredcites →https://doi.org/10.1145/859618.859642openalex-snapshot
Using destination-set prediction to improve the latency/bandwidth tradeoff in shared-memory multiprocessors
inferredcites →https://doi.org/10.1147/sj.71.0015openalex-snapshot
Structural aspects of the System/360 Model 85, II: The cache
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-662-44491-7_1openalex-snapshot
Fusion Coherence: Scalable Cache Coherence for Heterogeneous Kilo-Core System
inferred← citeshttps://doi.org/10.1007/s11227-013-0900-4openalex-snapshot
DP&TB: a coherence filtering protocol for many-core chip multiprocessors
inferred← citeshttps://doi.org/10.1007/s11432-014-5175-8openalex-snapshot
Improving multiprocessor performance with fine-grain coherence bypass
inferred← citeshttps://doi.org/10.1016/j.sysarc.2008.10.006openalex-snapshot
A framework for low energy data management in reconfigurable multi-context architectures
inferred← citeshttps://doi.org/10.1109/hpca.2008.4658649openalex-snapshot
Power-Efficient DRAM Speculation
inferred← citeshttps://doi.org/10.1109/hpca.2011.5749739openalex-snapshot
Efficient data streaming with on-chip accelerators: Opportunities and challenges
inferred← citeshttps://doi.org/10.1109/hpca.2016.7446089openalex-snapshot
Selective GPU caches to eliminate CPU-GPU HW cache coherence
inferred← citeshttps://doi.org/10.1109/hpca51647.2021.00060openalex-snapshot
Stream Floating: Enabling Proactive and Decentralized Cache Optimizations
inferred← citeshttps://doi.org/10.1109/isca45697.2020.00025openalex-snapshot
Efficiently Supporting Dynamic Task Parallelism on Heterogeneous Cache-Coherent Systems
inferred← citeshttps://doi.org/10.1109/micro.2008.4771777openalex-snapshot
Virtual tree coherence: Leveraging regions and in-network multicast trees for scalable cache coherence
inferred← citeshttps://doi.org/10.1109/micro.2008.4771796openalex-snapshot
Reducing the harmful effects of last-level cache polluters with an OS-level, software-only pollute buffer
inferred← citeshttps://doi.org/10.1109/pacrim.2009.5291238openalex-snapshot
Teaching old caches new tricks: RegionTracker and predictor virtualization
inferred← citeshttps://doi.org/10.1109/pact.2011.21openalex-snapshot
DeNovo: Rethinking the Memory Hierarchy for Disciplined Parallelism
inferred← citeshttps://doi.org/10.1109/samos.2012.6404165openalex-snapshot
Counting stream registers: An efficient and effective snoop filter architecture
inferred← citeshttps://doi.org/10.1109/tc.2011.241openalex-snapshot
Increasing the Effectiveness of Directory Caches by Avoiding the Tracking of Noncoherent Memory Blocks
inferred← citeshttps://doi.org/10.1145/1393921.1393988openalex-snapshot
Energy-efficient MESI cache coherence with pro-active snoop filtering for multicore microprocessors
inferred← citeshttps://doi.org/10.1145/1542275.1542288openalex-snapshot
Zero-content augmented caches
inferred← citeshttps://doi.org/10.1145/1669112.1669143openalex-snapshot
In-network coherence filtering
inferred← citeshttps://doi.org/10.1145/2000064.2000076openalex-snapshot
Increasing the effectiveness of directory caches by deactivating coherence for private memory blocks
inferred← citeshttps://doi.org/10.1145/2024723.2000076openalex-snapshot
Increasing the effectiveness of directory caches by deactivating coherence for private memory blocks
inferred← citeshttps://doi.org/10.1145/2245276.2232065openalex-snapshot
Reducing last level cache pollution through OS-level software-controlled region-based partitioning
inferred← citeshttps://doi.org/10.1145/2540708.2540747openalex-snapshot
Heterogeneous system coherence for integrated CPU-GPU systems
inferred← citeshttps://doi.org/10.1145/2678373.2665694openalex-snapshot
The Direct-to-Data (D2D) cache
inferred← citeshttps://doi.org/10.1145/2830772.2830774openalex-snapshot
Exploiting commutativity to reduce the cost of updates to shared data in cache-coherent systems
inferred← citeshttps://doi.org/10.1145/2989081.2989092openalex-snapshot
Software Assisted Hardware Cache Coherence for Heterogeneous Processors
inferred← citeshttps://doi.org/10.11606/d.3.2011.tde-31082011-163312openalex-snapshot
Power Laws na modelagem de caches de microprocessadores.
inferred← citeshttps://doi.org/10.1184/r1/6621872openalex-snapshot
DeNovo: Rethinking Hardware for Disciplined Parallelism
inferred← citeshttps://doi.org/10.5555/2485288.2485311openalex-snapshot
A dual grain hit-miss detector for large die-stacked DRAM caches
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