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Skewed Compressed Caches
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Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-44587-0_1openalex-snapshot
SPEComp: A New Benchmark Suite for Measuring Parallel Computer Performance
inferredcites →https://doi.org/10.1016/s1383-7621(00)00030-8openalex-snapshot
An on-chip cache compression technique to reduce decompression overhead and design complexity
inferredcites →https://doi.org/10.1109/hpca.2001.903253openalex-snapshot
Performance of hardware compressed main memory
inferredcites →https://doi.org/10.1109/hpca.2003.1183520openalex-snapshot
Variability in architectural simulations of multi-threaded workloads
inferredcites →https://doi.org/10.1109/hpca.2005.4openalex-snapshot
A Unified Compressed Memory Hierarchy
inferredcites →https://doi.org/10.1109/hpca.2013.6522313openalex-snapshot
ECM: Effective Capacity Maximizer for high-performance compressed caching
inferredcites →https://doi.org/10.1109/isca.1994.288133openalex-snapshot
Decoupled sectored caches: conciliating low tag implementation cost and low miss ratio
inferredcites →https://doi.org/10.1109/isca.2004.1310776openalex-snapshot
Adaptive cache compression for high-performance processors
inferredcites →https://doi.org/10.1109/isca.2005.6openalex-snapshot
A robust main-memory compression scheme
inferredcites →https://doi.org/10.1109/mc.2003.1178046openalex-snapshot
Simulating a $2M commercial server on a $2K PC
inferredcites →https://doi.org/10.1109/micro.2007.14openalex-snapshot
A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy
inferredcites →https://doi.org/10.1109/micro.2010.20openalex-snapshot
The ZCache: Decoupling Ways and Associativity
inferredcites →https://doi.org/10.1109/mm.2014.42openalex-snapshot
Decoupled Compressed Cache: Exploiting Spatial Locality for Energy Optimization
inferredcites →https://doi.org/10.1109/tc.2004.21openalex-snapshot
Concurrent support of multiple page sizes on a skewed associative TLB
inferredcites →https://doi.org/10.1109/tvlsi.2009.2020989openalex-snapshot
C-Pack: A High-Performance Microprocessor Cache Compression Algorithm
inferredcites →https://doi.org/10.1145/1028176.1006719openalex-snapshot
Adaptive Cache Compression for High-Performance Processors
inferredcites →https://doi.org/10.1145/1080695.1069978openalex-snapshot
A Robust Main-Memory Compression Scheme
inferredcites →https://doi.org/10.1145/1105734.1105747openalex-snapshot
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
inferredcites →https://doi.org/10.1145/1542275.1542288openalex-snapshot
Zero-content augmented caches
inferredcites →https://doi.org/10.1145/165123.165152openalex-snapshot
A case for two-way skewed-associative caches
inferredcites →https://doi.org/10.1145/191995.192072openalex-snapshot
Decoupled sectored caches: conciliating low tag implementation cost
inferredcites →https://doi.org/10.1145/1944862.1944876openalex-snapshot
Decoupled zero-compressed memory
inferredcites →https://doi.org/10.1145/305138.305156openalex-snapshot
The pool of subsectors cache design
inferredcites →https://doi.org/10.1145/360128.360150openalex-snapshot
Dynamic zero compression for cache energy reduction
inferredcites →https://doi.org/10.1145/581888.581894openalex-snapshot
Frequent value locality and its applications
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-030-88040-8_11openalex-snapshot
An Investigation of Microarchitectural Cache-Based Side-Channel Attacks from a Digital Forensic Perspective: Methods of Exploits and Countermeasures
inferred← citeshttps://doi.org/10.1007/978-3-031-04580-6_5openalex-snapshot
A Case for Partial Co-allocation Constraints in Compressed Caches
inferred← citeshttps://doi.org/10.1007/978-3-319-99322-5_20openalex-snapshot
Approximate Cache Architectures
inferred← citeshttps://doi.org/10.1109/dsn.2019.00048openalex-snapshot
SuDoku: Tolerating High-Rate of Transient Failures for Enabling Scalable STTRAM
inferred← citeshttps://doi.org/10.1109/hpca.2016.7446064openalex-snapshot
A case for toggle-aware compression for GPU systems
inferred← citeshttps://doi.org/10.1109/hpca.2018.00028openalex-snapshot
LATTE-CC: Latency Tolerance Aware Adaptive Cache Compression Management for Energy Efficient GPUs
inferred← citeshttps://doi.org/10.1109/hpca.2019.00010openalex-snapshot
Enabling Transparent Memory-Compression for Commodity Memory Systems
inferred← citeshttps://doi.org/10.1109/hpca56546.2023.10071115openalex-snapshot
Baryon: Efficient Hybrid Memory Management with Compression and Sub-Blocking
inferred← citeshttps://doi.org/10.1109/hpca57654.2024.00080openalex-snapshot
Enterprise-Class Cache Compression Design
inferred← citeshttps://doi.org/10.1109/hpca68181.2026.11408535openalex-snapshot
Intermittence-Aware Cache Compression
inferred← citeshttps://doi.org/10.1109/hpcc-dss-smartcity-dependsys53884.2021.00110openalex-snapshot
Reinforcement Learning based Data Compression for Energy-Efficient Non-volatile Caches
inferred← citeshttps://doi.org/10.1109/iccd.2017.61openalex-snapshot
Dual Dictionary Compression for the Last Level Cache
inferred← citeshttps://doi.org/10.1109/iccd46524.2019.00040openalex-snapshot
NVDL-Cache: Narrow-Width Value Aware Variable Delay Low-Power Data Cache
inferred← citeshttps://doi.org/10.1109/iccd56317.2022.00018openalex-snapshot
SLAP-CC: Set-Level Adaptive Prefetching for Compressed Caches
inferred← citeshttps://doi.org/10.1109/isca.2016.36openalex-snapshot
Base-Victim Compression: An Opportunistic Cache Compression Architecture
inferred← citeshttps://doi.org/10.1109/jssc.2018.2837124openalex-snapshot
A Fully Integrated Energy-Efficient H.265/HEVC Decoder With eDRAM for Wearable Devices
inferred← citeshttps://doi.org/10.1109/micro.2016.7783704openalex-snapshot
Dictionary sharing: An efficient cache compression scheme for compressed caches
inferred← citeshttps://doi.org/10.1109/micro.2016.7783744openalex-snapshot
Concise loads and stores: The case for an asymmetric compute-memory architecture for approximation
inferred← citeshttps://doi.org/10.1109/micro.2018.00033openalex-snapshot
CABLE: A CAche-Based Link Encoder for Bandwidth-Starved Manycores
inferred← citeshttps://doi.org/10.1109/micro.2018.00034openalex-snapshot
Attaché: Towards Ideal Memory Compression by Mitigating Metadata Bandwidth Overheads
inferred← citeshttps://doi.org/10.1109/micro50266.2020.00025openalex-snapshot
Improving the Utilization of Micro-operation Caches in x86 Processors
inferred← citeshttps://doi.org/10.1109/nas51552.2021.9605440openalex-snapshot
Cache Compression with Efficient in-SRAM Data Comparison
inferred← citeshttps://doi.org/10.1109/padsw.2018.8644558openalex-snapshot
Data Locality Exploitation in Cache Compression
inferred← citeshttps://doi.org/10.1109/sbac-pad.2019.00017openalex-snapshot
Compressed Cache Layout Aware Prefetching
inferred← citeshttps://doi.org/10.1109/sp40001.2021.00050openalex-snapshot
Randomized Last-Level Caches Are Still Vulnerable to Cache Side-Channel Attacks! But We Can Fix It
inferred← citeshttps://doi.org/10.1109/sp46215.2023.10179440openalex-snapshot
Scatter and Split Securely: Defeating Cache Contention and Occupancy Attacks
inferred← citeshttps://doi.org/10.1109/tc.2015.2479585openalex-snapshot
Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage
inferred← citeshttps://doi.org/10.1109/tc.2019.2939809openalex-snapshot
Scrabble: A Fine-Grained Cache with Adaptive Merged Block
inferred← citeshttps://doi.org/10.1109/tc.2024.3441835openalex-snapshot
A Parallel Tag Cache for Hardware Managed Tagged Memory in Multicore Processors
inferred← citeshttps://doi.org/10.1109/tpds.2015.2435788openalex-snapshot
A Survey Of Architectural Approaches for Data Compression in Cache and Main Memory Systems
inferred← citeshttps://doi.org/10.1109/tpds.2017.2763141openalex-snapshot
Alleviating Memory Refresh Overhead via Data Compression for High Performance and Energy Efficiency
inferred← citeshttps://doi.org/10.1109/tpds.2017.2773516openalex-snapshot
IBOM: An Integrated and Balanced On-Chip Memory for High Performance GPGPUs
inferred← citeshttps://doi.org/10.1145/3132402.3132411openalex-snapshot
Composing lifetime enhancing techniques for non-volatile main memories
inferred← citeshttps://doi.org/10.1145/3138805openalex-snapshot
Could Compression Be of General Use? Evaluating Memory Compression across Domains
inferred← citeshttps://doi.org/10.1145/3240302.3240429openalex-snapshot
Opportunistic compression for direct-mapped DRAM caches
inferred← citeshttps://doi.org/10.1145/3243176.3243178openalex-snapshot
Synergistic cache layout for reuse and compression
inferred← citeshttps://doi.org/10.1145/3297858.3304006openalex-snapshot
Compress Objects, Not Cache Lines
inferred← citeshttps://doi.org/10.1145/3307650.3322246openalex-snapshot
New attacks and defense for encrypted-address cache
inferred← citeshttps://doi.org/10.1145/3373376.3378453openalex-snapshot
Safecracker: Leaking Secrets through Compressed Caches
inferred← citeshttps://doi.org/10.1145/3721286openalex-snapshot
TSN Cache: Exploiting Data Localities in Graph Computing Applications
inferred← citeshttps://doi.org/10.1145/3725843.3756040openalex-snapshot
SeaCache: Efficient and Adaptive Caching for Sparse Accelerators
inferred← citeshttps://doi.org/10.17760/d20316358openalex-snapshot
Exploring compression in the GPU memory hierarchy for graphics and compute
inferred← citeshttps://doi.org/10.2200/s00683ed1v01y201511cac036openalex-snapshot
A Primer on Compression in the Memory Hierarchy
inferred← citeshttps://doi.org/10.3390/electronics11020240openalex-snapshot
Exploiting Data Compression for Adaptive Block Placement in Hybrid Caches
inferred← citeshttps://doi.org/10.3390/electronics13071185openalex-snapshot
Enhancing Power Efficiency in Branch Target Buffer Design with a Two-Level Prediction Mechanism
inferred← citeshttps://doi.org/10.46586/tches.v2022.i3.1-25openalex-snapshot
Security Model for Randomization-based Protected Caches
inferred← citeshttps://doi.org/10.48550/arxiv.1609.02067openalex-snapshot
Practical Data Compression for Modern Memory Hierarchies
inferred← citeshttps://doi.org/10.48550/arxiv.1704.03991openalex-snapshot
Architectural Techniques to Enable Reliable and Scalable Memory Systems
inferred← citeshttps://doi.org/10.5555/3195638.3195688openalex-snapshot
Concise loads and stores: the case for an asymmetric compute-memory architecture for approximation
inferred← citeshttps://doi.org/10.70675/22db70b0z0f98z4fbez90cezf8c8729e2ea5openalex-snapshot
Compressed cache layout aware prefetching
inferred← citeshttps://doi.org/10.70675/ff9a8713ze4f9z421ez8b99zdfef9781d066openalex-snapshot
Towards compression at all levels in the memory hierarchy
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