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Flexible and Efficient Instruction-Grained Run-Time Monitoring Using On-Chip Reconfigurable Fabric
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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OneChip: an FPGA processor with reconfigurable logic
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Garp: a MIPS processor with a reconfigurable coprocessor
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Post-silicon debug using programmable logic cores
inferredcites →https://doi.org/10.1109/hpca.2007.346205openalex-snapshot
MemTracker: Efficient and Programmable Support for Memory Access Monitoring and Debugging
inferredcites →https://doi.org/10.1109/hpca.2008.4658637openalex-snapshot
FlexiTaint: A programmable accelerator for dynamic taint propagation
inferredcites →https://doi.org/10.1109/isca.2008.20openalex-snapshot
Flexible Hardware Acceleration for Instruction-Grain Program Monitoring
inferredcites →https://doi.org/10.1109/micro.1999.809458openalex-snapshot
DIVA: a reliable substrate for deep submicron microarchitecture design
inferredcites →https://doi.org/10.1109/micro.2004.26openalex-snapshot
Minos: Control Data Attack Prevention Orthogonal to Memory Model
inferredcites →https://doi.org/10.1109/micro.2006.29openalex-snapshot
LIFT: A Low-Overhead Practical Information Flow Tracking System for Detecting Security Attacks
inferredcites →https://doi.org/10.1109/micro.2007.18openalex-snapshot
Argus: Low-Cost, Comprehensive Error Detection in Simple Cores
inferredcites →https://doi.org/10.1109/micro.2007.8openalex-snapshot
40th Annual IEEE/ACM International Symposium on Microarchitecture - Table of Contents
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Preventing Memory Error Exploits with WIT
inferredcites →https://doi.org/10.1109/tvlsi.2003.821545openalex-snapshot
The Chimaera reconfigurable functional unit
inferredcites →https://doi.org/10.1109/wwc.2001.15openalex-snapshot
MiBench: A free, commercially representative embedded benchmark suite
inferredcites →https://doi.org/10.1109/wwc.2001.990739openalex-snapshot
MiBench: A free, commercially representative embedded benchmark suite
inferredcites →https://doi.org/10.1145/1024393.1024404openalex-snapshot
Secure program execution via dynamic information flow tracking
inferredcites →https://doi.org/10.1145/1134285.1134309openalex-snapshot
Backwards-compatible array bounds checking for C with very low overhead
inferredcites →https://doi.org/10.1145/1146909.1146916openalex-snapshot
A reconfigurable design-for-debug infrastructure for SoCs
inferredcites →https://doi.org/10.1145/1146909.1146998openalex-snapshot
Shielding against design flaws with field repairable control logic
inferredcites →https://doi.org/10.1145/1150019.1136520openalex-snapshot
An Integrated Framework for Dependable and Revivable Architectures Using Multicore Processors
inferredcites →https://doi.org/10.1145/1321631.1321673openalex-snapshot
Effective memory protection using dynamic tainting
inferredcites →https://doi.org/10.1145/1344671.1344695openalex-snapshot
Area and delay trade-offs in the circuit and architecture design of FPGAs
inferredcites →https://doi.org/10.1145/1394608.1382153openalex-snapshot
Flexible Hardware Acceleration for Instruction-Grain Program Monitoring
inferredcites →https://doi.org/10.1145/1555754.1555806openalex-snapshot
Flexible reference-counting-based hardware acceleration for garbage collection
inferredcites →https://doi.org/10.1145/1669112.1669161openalex-snapshot
Ordering decoupled metadata accesses in multiprocessors
inferredcites →https://doi.org/10.1145/192724.192749openalex-snapshot
A high-performance microarchitecture with hardware-programmable functional units
inferredcites →https://doi.org/10.1145/329166.329185openalex-snapshot
A reconfigurable multi-function computing cache architecture
inferredcites →https://doi.org/10.1145/859618.859633openalex-snapshot
A "flight data recorder" for enabling full-system multiprocessor deterministic replay
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Sidecar: Leveraging Debugging Extensions in Commodity Processors to Secure Software
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WHISK: An uncore architecture for Dynamic Information Flow Tracking in heterogeneous embedded SoCs
inferred← citeshttps://doi.org/10.1109/dac63849.2025.11133122openalex-snapshot
FireGuard: A Generalized Microarchitecture for Fine-Grained Security Analysis on OoO Superscalar Cores
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An Architecture to Enable Life Cycle Testing in CMPs
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High-performance parallel accelerator for flexible and efficient run-time monitoring
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Towards a hardware-assisted information flow tracking ecosystem for ARM processors
inferred← citeshttps://doi.org/10.1109/hpca.2014.6835922openalex-snapshot
FADE: A programmable filtering accelerator for instruction-grain monitoring
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NDA: Near-DRAM acceleration architecture leveraging commodity DRAM devices and standard memory modules
inferred← citeshttps://doi.org/10.1109/hpca.2015.7056071openalex-snapshot
Run-time monitoring with adjustable overhead using dataflow-guided filtering
inferred← citeshttps://doi.org/10.1109/iccd.2011.6081438openalex-snapshot
Precise exception support for decoupled run-time monitoring architectures
inferred← citeshttps://doi.org/10.1109/iccd.2012.6378669openalex-snapshot
Fast development of hardware-based run-time monitors through architecture framework and high-level synthesis
inferred← citeshttps://doi.org/10.1109/iccd65941.2025.00101openalex-snapshot
Design and Evaluation of an N-Trace Compliant Hardware Tracer for RISC-V Processors
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Out-of-order execution on reconfigurable heterogeneous MPSOC using particle swarm optimization
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Detecting Data Hazards in Multi-Processor System-on-Chips on FPGA
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FPM: A Flexible Programming Model for MPSoC on FPGA
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Enabling Continuous, in-Field Introspection: The Programmable IPU Architecture
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Enforcing security for real-time multicore embedded system
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Jintide: Utilizing Low-Cost Reconfigurable External Monitors to Substantially Enhance Hardware Security of Large-Scale CPU Clusters
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Nile: A Programmable Monitoring Coprocessor
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Speculative Taint Tracking (STT): A Comprehensive Protection for Speculatively Accessed Data
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A small and adaptive coprocessor for information flow tracking in ARM SoCs
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SecureCore: A multicore-based intrusion detection architecture for real-time embedded systems
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Slack-aware opportunistic monitoring for real-time systems
inferred← citeshttps://doi.org/10.1109/tc.2012.189openalex-snapshot
SIFT: Low-Complexity Energy-Efficient Information Flow Tracking on SMT Processors
inferred← citeshttps://doi.org/10.1109/tc.2014.2315628openalex-snapshot
Architecture Support for Task Out-of-Order Execution in MPSoCs
inferred← citeshttps://doi.org/10.1109/tc.2022.3180990openalex-snapshot
WHISTLE: CPU Abstractions for Hardware and Software Memory Safety Invariants
inferred← citeshttps://doi.org/10.1109/tcad.2018.2857321openalex-snapshot
PAGURUS: Low-Overhead Dynamic Information Flow Tracking on Loosely Coupled Accelerators
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Hardware-Supported Patching of Security Bugs in Hardware IP Blocks
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FineDIFT: Fine-Grained Dynamic Information Flow Tracking for Data-Flow Integrity Using Coprocessor
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A Ubiquitous Machine Learning Accelerator With Automatic Parallelization on FPGA
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Static or Dynamic: Trade-Offs for Task Dependency Analysis for Heterogeneous MPSoC
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SOLAR: Services-oriented Deep Learning Architectures
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Evaluation and Tradeoffs for Out-of-Order Execution on Reconfigurable Heterogeneous MPSoC
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Worst-case execution time analysis for parallel run-time monitoring
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Micro-architectural support for metadata coherence in multi-core dynamic information flow tracking
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A verified information-flow architecture
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Implementing an Application-Specific Instruction-Set Processor for System-Level Dynamic Program Analysis Engines
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Efficient Security Monitoring with the Core Debug Interface in an Embedded Processor
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Architectural Support for Containment-based Security
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Building a portable deeply-nested implicit information flow tracking
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HerQules: securing programs via hardware-enforced message queues
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Architectural support for software security
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A verified information-flow architecture
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TrackRISC: An Implicit Attack Flow Model and Hardware Microarchitectural Mitigation for Speculative Cache-Based Covert Channels
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S3A: Secure System Simplex Architecture for Enhanced Security of Cyber-Physical Systems
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Architectural Support to Accelerate Fine-Grain Program Monitoring
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