On the public citation graph

FPM: A Flexible Programming Model for MPSoC on FPGA

0 signed · 30 inferred · view as graph

Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

Is this your work? Sign in with ORCID and put your name on the claims that are yours.
Claim with ORCID
Reference health. See whether every reference in this work resolves to a known work and none has been retracted — and get a dated CiteStamped badge you can embed.
See reference health

What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1006/jpdc.1996.0107openalex-snapshot
Cilk: An Efficient Multithreaded Runtime System
inferredcites →https://doi.org/10.1007/s11265-007-0138-6openalex-snapshot
A Distributed, Simultaneously Multi-Threaded (SMT) Processor with Clustered Scheduling Windows for Scalable DSP Performance
inferredcites →https://doi.org/10.1016/0026-2692(93)90111-qopenalex-snapshot
Computer architecture: a quantitative approach
inferredcites →https://doi.org/10.1109/fccm.2009.7openalex-snapshot
Design Exploration for FPGA-Based Multiprocessor Architecture: JPEG Encoding Case Study
inferredcites →https://doi.org/10.1109/ispa.2011.40openalex-snapshot
A Flexible High Speed Star Network Based on Peer to Peer Links on FPGA
inferredcites →https://doi.org/10.1109/micro.2010.13openalex-snapshot
Task Superscalar: An Out-of-Order Task Pipeline
inferredcites →https://doi.org/10.1109/micro.2010.17openalex-snapshot
Flexible and Efficient Instruction-Grained Run-Time Monitoring Using On-Chip Reconfigurable Fabric
inferredcites →https://doi.org/10.1109/micro.2010.27openalex-snapshot
Automatic Parallelization in a Binary Rewriter
inferredcites →https://doi.org/10.1109/pact.2007.4336196openalex-snapshot
A Flexible Heterogeneous Multi-Core Architecture
inferredcites →https://doi.org/10.1109/scc.2011.26openalex-snapshot
SOMP: Service-Oriented Multi Processors
inferredcites →https://doi.org/10.1145/1555815.1555763openalex-snapshot
Dynamic MIPS rate stabilization in out-of-order processors
inferredcites →https://doi.org/10.1145/1941487.1941507openalex-snapshot
The future of microprocessors
inferredcites →https://doi.org/10.1145/1978542.1978558openalex-snapshot
Computing without processors
inferredcites →https://doi.org/10.1147/rd.111.0025openalex-snapshot
An Efficient Algorithm for Exploiting Multiple Arithmetic Units
inferredcites →https://doi.org/10.1177/1094342009106195openalex-snapshot
Hierarchical Task-Based Programming With StarSs

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-319-05960-0_33openalex-snapshot
Instruction Extension and Generation for Adaptive Processors
inferred← citeshttps://doi.org/10.1007/s11227-021-03792-7openalex-snapshot
Efficient heterogeneous programming with FPGAs using the Controller model
inferred← citeshttps://doi.org/10.1080/00207217.2014.938312openalex-snapshot
Codem: software/hardware codesign for embedded multicore systems supporting hardware services
inferred← citeshttps://doi.org/10.1109/fpl.2012.6339263openalex-snapshot
CaaS: Core as a service realizing hardware sercices on reconfigurable MPSoCS
inferred← citeshttps://doi.org/10.1109/fpt.2012.6412107openalex-snapshot
A task-level OoO framework for heterogeneous systems
inferred← citeshttps://doi.org/10.1109/fpt.2012.6412111openalex-snapshot
Parallel dataflow execution for sequential programs on reconfigurable hybrid MPSoCs
inferred← citeshttps://doi.org/10.1109/icws.2016.29openalex-snapshot
FairPlay: Services Migration with Lock-Free Mechanisms for Load Balancing in Cloud Architectures
inferred← citeshttps://doi.org/10.1109/recosoc.2016.7533911openalex-snapshot
A programming model for reconfigurable computing based in functional concurrency
inferred← citeshttps://doi.org/10.1109/tc.2014.2315628openalex-snapshot
Architecture Support for Task Out-of-Order Execution in MPSoCs
inferred← citeshttps://doi.org/10.1109/tcbb.2019.2947059openalex-snapshot
GenSeq+: A Scalable High-Performance Accelerator for Genome Sequencing
inferred← citeshttps://doi.org/10.1109/trustcom.2013.110openalex-snapshot
Static or Dynamic: Trade-Offs for Task Dependency Analysis for Heterogeneous MPSoC
inferred← citeshttps://doi.org/10.1109/trustcom.2016.0193openalex-snapshot
SCADIS: A Scalable Accelerator for Data-Intensive String Set Matching on FPGAs
inferred← citeshttps://doi.org/10.1145/2459316.2459320openalex-snapshot
MP-Tomasulo
inferred← citeshttps://doi.org/10.1145/3479394.3479417openalex-snapshot
A Mechanized Semantic Metalanguage for High Level Synthesis
inferred← citeshttps://doi.org/10.1504/ijhpsa.2014.061466openalex-snapshot
Amdahl's and Hill-Marty laws revisited for FPGA-based MPSoCs: from theory to practice
Editorial review for independent work. ICSAC — the Institute for Complexity Science and Advanced Computing — runs a structured editorial panel for researchers publishing outside journals, and publishes on CiteStamp rails. Submission is free and goes through ORCID: icsacinstitute.org/submit.